Understanding Setup and Hold Time Violations in PrimeTime
If you are new to timing closure, setup and hold violations are the two things you will spend most of your days chasing. I want to walk you through them the way I would explain it to a junior engineer sitting next to me, not the way a textbook does.
Both checks are about one question. Did the data arrive at the flip-flop at the right time relative to the clock edge. Setup and hold are just the two halves of that question.
Setup, in plain terms
A flip-flop captures data on a clock edge. For that capture to be reliable, the data has to be stable for a small window before the edge arrives. That window is the setup time of the flop.
If the data is still changing when the edge comes, the flop may capture the wrong value, or worse, go metastable. Setup says the data must arrive early enough. The path from the launching flop, through the logic, to the capturing flop must be fast enough to finish before the next edge minus the setup time.
When setup fails, the path is too slow. Either the logic between the flops is too deep, or the clock is too fast for it. This is the comfortable kind of violation, because you can always slow the clock down and it goes away.
Hold, and why it is scarier
Hold is the other side. After the clock edge captures data, that data must stay stable for a small window after the edge. That window is the hold time.
A hold violation means new data raced through the logic and reached the capturing flop too soon, corrupting the value that was just captured. The key thing to understand is that hold does not depend on the clock period. Slowing the clock does nothing, because the race is between the data and the same edge that just captured.
That is what makes hold violations dangerous. If a hold violation reaches silicon, you cannot slow the clock to escape it. The chip is simply broken at that path. This is why hold is signed off at the fast process corner, where cells are quickest and the race is tightest.
Reading them in PrimeTime
In PrimeTime you look at these with report_timing. For a setup check you ask for the maximum delay path. For hold you ask for the minimum delay path. Here is the command I reach for first.
# Worst setup path to a specific endpoint
report_timing -delay_type max \
-to [get_pins core/data_reg*/D] \
-max_paths 5 -nworst 2
# Worst hold path, fast corner
report_timing -delay_type min \
-to [get_pins core/data_reg*/D] \
-max_paths 5The report walks the path cell by cell. The number that matters at the bottom is the slack. Positive slack means the path passes. Negative slack means it fails by that amount, and that amount tells you how much work you have to do.
Setup versus hold, side by side
When you are deep in a closure cycle it helps to keep the differences straight. This is the table I wish someone had handed me on day one.
| Setup | Hold | |
|---|---|---|
| What it checks | Data arrives before the edge | Data stays stable after the edge |
| Failure means | Path is too slow | Path is too fast |
| Depends on clock period | Yes | No |
| Signoff corner | Slow process | Fast process |
| Typical fix | Faster cells, less logic, slower clock | Add buffers or delay cells on the path |
| Reachable on silicon | Yes, drop the frequency | No, the chip is broken |
When you fix a hold violation by adding delay cells, re-run setup on that same path afterward. The delay you added for hold eats into your setup margin. On a tight path you can trade one violation for the other if you are not watching both.
A typical closure cycle
In practice you close setup first, across the slow corners, by speeding up paths and letting the tool optimize. Once setup is stable, you turn to hold at the fast corner.
Hold fixes are mostly mechanical. The tool inserts buffers or delay cells on the fast paths to slow the data down just enough. Because hold fixes add cells, they can create new congestion or nudge setup, so you iterate until both checks are clean at every corner.
Do not close hold before the clock tree is built. Before CTS the clock is ideal and your hold numbers are fiction. CTS introduces real skew, and that is exactly when most hold violations appear. Fixing hold on an ideal clock is wasted work.
The mental model to keep
Hold these two sentences in your head and most timing work makes sense. Setup is the data being too slow, and you have the clock period to play with. Hold is the data being too fast, and the clock period cannot help you.
Once that clicks, a timing report stops being a wall of numbers and becomes a clear instruction. Speed this path up, or slow that one down. Everything else is detail.