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VLSI Physical Design

Algorithms, Methodology, and the RTL-to-GDSII Flow

PHV · First Edition, 2026 · ISBN 978-93-6038-627-6

A complete, working reference for physical design: how a netlist becomes a manufacturable layout, why each step exists, and what actually goes wrong in production. Written for engineers who need the reasoning behind the flow, not just the commands.

What is inside

• Nine chapters, ~86,000 words, from partitioning to signoff
• Algorithms explained with the intuition first, then the formal method
• The full RTL-to-GDSII production flow as it runs in industry
• Timing closure treated as its own chapter, in depth
• Diagrams drawn for the page, not stock illustrations

Contents

1. 1IntroductionRead free
2. 2Netlist and System Partitioning8,724 words
3. 3Chip Planning: Floorplanning, Pin Assignment & Power/Ground9,732 words
4. 4Global and Detailed Placement9,096 words
5. 5Global Routing11,179 words
6. 6Detailed Routing6,039 words
7. 7Specialized Routing & Clock Tree Synthesis8,049 words
8. 8Timing Closure13,983 words
9. 9The Modern Production Flow (RTL to GDSII)8,358 words

Who it is for

• Engineers moving into backend or physical design roles
• PD engineers who know the commands but want the reasoning
• Final-year and postgraduate students in VLSI

Before you buy

• This is the e-book. You read it in your browser on any device, signed in to your SiliconPath account.
• There is no PDF or download, and it cannot be printed.
• Front matter and Chapter 1 are free to read before you buy.
• One-time payment. No expiry, no subscription.

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