Learning Paths

Number systems, gates, Boolean algebra, K-maps, and sequential logic — the foundation under every chip.

Turn RTL into a gate-level netlist. Constraints, mapping, and quality of results.

RTL to GDSII on a real flow. Floorplanning, placement, CTS, routing, and signoff.

Setup, hold, clocks, and signoff with PrimeTime. The language of timing closure.

DRC, LVS, and antenna checks. Prove the layout is manufacturable and matches intent.

Cut dynamic and leakage power: clock gating, multi-Vt, power domains, and UPF intent.

90+ real VLSI interview questions across Synthesis, PD and STA, with a cheatsheet and glossary.

Pick your domain, follow a fresher-to-pro learning path, and prep with an 8-week plan.