Design for Test
Every manufactured chip must be tested for physical defects, and Design for Test is the logic and methodology that makes it possible. This path covers testability from the ground up: verification versus test, fault models and coverage, scan design, automatic test pattern generation, scan compression, memory BIST, and boundary scan with JTAG, plus where DFT fits in the flow.
8 modulesIntermediateScanATPGJTAG
1
Why Design for Test Exists
Catching manufacturing defects in real silicon
7 minFree
2
Fault Models and Coverage
How we model physical defects as testable faults
8 minFree
3
Scan Design
Turning every flip-flop into a test point
10 minFree
4
ATPG: Generating the Patterns
How test patterns are created automatically
9 minFree
5
Scan Compression
Cutting test time and test data
7 minFree
6
Memory BIST
Testing on-chip memories from the inside
8 minFree
7
Boundary Scan and JTAG
Testing the connections between chips
8 minFree
8
DFT in the Design Flow
Where DFT fits, and the rules that make it work
7 minFree