ATPG: Generating the Patterns

Once a design has scan chains, you need the actual test patterns to shift in. Writing them by hand is impossible, so a tool generates them automatically. This is ATPG, Automatic Test Pattern Generation.

What ATPG does

The ATPG tool takes the gate-level netlist and the fault list and, for each fault, computes an input pattern that will both activate the fault (drive the node to the opposite value) and propagate its effect to a scan flop or output where it can be observed. It does this for the whole fault list and produces a compact set of patterns.

Activate and propagate

Every pattern does the two things from the fault-model lesson. To test a node for stuck-at-0, the tool sets that node to 1 (activate) and steers the surrounding logic so that the 1, or its corruption to 0 if the fault is present, reaches an observable point (propagate). Scan makes both steps easy because every flop is directly loadable and readable.

Test compaction

A single clever pattern can detect many faults at once. The tool compacts patterns so that the final set detects as many faults as possible with as few patterns as possible, because fewer patterns means less test time and less test data on the tester.

Stuck-at and at-speed patterns

• Stuck-at patterns catch permanently broken nodes and are shifted and captured at low speed.
• At-speed patterns (transition fault patterns) catch nodes that switch too slowly. They use two rapid capture clocks so the logic must transition at full speed, exposing timing defects.