Memory BIST
Testing on-chip memories from the inside
Scan and ATPG test the logic, but on-chip memories need their own approach. Memories are dense, regular arrays with failure modes that scan cannot reach well, so we test them with built-in self-test, or MBIST.
Why memories are special
A RAM is a tightly packed array of cells with defects all its own: a cell stuck at a value, two adjacent cells that interfere, a cell that fails only after a neighbor is written. Shifting patterns through scan cannot exercise these patterns efficiently. Instead we put a small test engine right next to the memory.
How MBIST works
An MBIST controller is a piece of logic built into the chip beside each memory. When test mode is entered, it writes and reads a structured sequence of values to every address at full speed, checks the results itself, and reports a simple pass or fail. Because it lives on-chip and runs at speed, it is fast and needs very little tester involvement.
March algorithms
MBIST uses march tests: defined sequences of writes and reads that march through every address in order, then in reverse, with specific value patterns. These sequences are designed to catch the classic memory faults, including ones where writing one cell disturbs another.
- Stuck-at cells: a bit that cannot change value.
- Transition faults: a cell that cannot make a particular 0-to-1 or 1-to-0 change.
- Coupling faults: writing one cell wrongly affects another.
- Address faults: an address that reaches the wrong cell.
memories can also include built-in repair (BISR): spare rows or columns that replace defective ones, so a chip with a few bad memory cells can still be sold instead of scrapped. Pairing MBIST with repair raises yield, which is real money on large memories.
MBIST must run at the memory operating speed to catch timing-related cell faults, so its clocking is part of DFT planning, not an afterthought. Plan the BIST clocks alongside the functional ones.