Blog
Notes on physical design, timing, and the EDA tools you use every day.
Understanding Setup and Hold Time Violations in PrimeTime
Setup and hold are the two halves of one question: did the data arrive at the flop at the right time. Here is how to read both in PrimeTime, and why hold is the one that should scare you.
Read →ICC2 Floorplanning: Where Most Engineers Go Wrong
A surprising number of backend problems are floorplan problems wearing a disguise. These are the macro placement and channel mistakes I see most often in ICC2.
Read →What is CTS and Why Does It Matter
Clock tree synthesis turns your ideal clock into a real one, and that is where hold violations are born. A plain explanation of skew, latency, and why CTS changes your timing.
Read →Timing Closure at 7nm: Key Differences from 28nm
Closing timing at 7nm is not 28nm with smaller numbers. Variation, crosstalk, and via resistance all change the game. Here is what actually shifts.
Read →How to Read a PrimeTime Timing Report
A timing report is a story about one path. Once you know how to read it line by line, debugging any violation becomes a matter of following the trail.
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