Routing in VLSI, Explained
Routing is the step that connects everything. After placement and clock tree synthesis, every net is still just a logical connection. Routing turns those connections into actual metal wires and vias on the chip, while obeying thousands of manufacturing rules. It happens in two stages, and knowing the difference clears up most confusion.
Global routing
Global routing does not draw real wires yet. It divides the chip into a grid of cells and decides, for each net, roughly which path and which metal layers it will take. Its real job is to balance demand against the available tracks so no region is over-congested. The output is a set of routing guides for the next stage.
Detailed routing
Detailed routing lays down the actual metal segments and vias inside the guides global routing produced, obeying every design rule: spacing, width, via rules, and more. This is where DRC violations are fixed, iteration by iteration, until the layout is clean and manufacturable.
| Global routing | Detailed routing | |
|---|---|---|
| Output | Routing guides per net | Real metal and vias |
| Main concern | Congestion and layer balance | Design-rule-clean connections |
| Granularity | Coarse, grid of cells | Exact tracks and vias |
Layers and directions
Metal layers alternate preferred directions, horizontal on one layer and vertical on the next, so wires on adjacent layers cross cleanly and connect through vias. Lower layers are thin and dense for local connections, upper layers are thick and low-resistance for long routes and power.
Special nets get special rules
Clock and other critical nets often use non-default rules, wider wires or extra spacing, and may be shielded to protect them from crosstalk. The router treats these differently from ordinary signal nets because their integrity matters more.
Congestion you see in routing was usually created in the floorplan or placement. If detailed routing cannot finish, the fix is often upstream, in utilization or macro placement, not in the router settings.
Watch for antenna violations during routing. Long metal segments connected to a gate can accumulate charge during manufacturing and damage the gate oxide. The router fixes these with diodes or by jumping layers, but they have to be addressed before signoff.
Key takeaways
- Global routing plans paths and balances congestion, detailed routing draws real metal
- Layers alternate preferred directions and connect through vias
- Clock and critical nets use non-default rules and shielding
- Most routing congestion is really a floorplan or placement problem