Synthesis
Logic synthesis is where RTL becomes gates. This path covers how Design Compiler and Genus read your RTL, apply constraints, map to a standard cell library, and optimize for timing, area, and power. You learn to write clean SDC and read synthesis QoR like an engineer who has shipped silicon.
Introduction to Synthesis
Key Terms - Defined Before We Go Further
Detailed Synthesis Flow
RTL to gate-level netlist stage by stage: read, elaborate (GTECH), logic optimization, technology mapping, post-map optimization, and formal equivalence.
Synopsys Design Compiler (DC)
The Design Compiler flow: libraries, read/elaborate, constrain, compile_ultra, report and write out; topographical mode and Fusion Compiler.
Cadence Genus
The Genus flow as explicit generic to mapped to optimized stages, its common UI with Innovus, and iSpatial physical synthesis.
Timing Constraints (SDC)
The SDC timing contract: clocks (create_clock, generated, virtual), input/output delay and the I/O budget, uncertainty and latency (pre/post-CTS), exceptions, clock groups and case analysis.
Optimization Techniques
Trading timing, area and power across the three optimization passes: restructuring, sizing, buffering, cloning, resource sharing, clock gating, multi-Vt and DRC fixing.
Quality of Results (QoR)
Reading QoR across timing (WNS/TNS/WHS + the slack histogram), area, power and design-rule legality, how to read report_qor, and fixing QoR in priority order.
Retiming: Moving Registers to Balance Logic
Relocating flops across logic to shorten the critical path
Hierarchy: Ungroup, Flatten, and Boundary Optimization
When to dissolve module boundaries and when to keep them
Power-Aware Synthesis: Clock Gating and Multi-Vt
Cutting dynamic power with gating and leakage with cell swaps
DFT and Scan-Aware Synthesis
Building testable logic by stitching flops into scan chains