Introduction to Synthesis
Key Terms - Defined Before We Go Further
Start Here - What Is RTL? — RTL (Register Transfer Level) is the way engineers describe digital hardware in code - using languages like Verilog or VHDL. You write what the circuit does (assign outputs = inputs AND enable, always @posedge clk...) without specifying exactly which physical transistors to use. Think of it like a recipe - RTL is the recipe, silicon transistors are the actual ingredients. Synthesis is the chef that takes that recipe and builds the real thing from whatever physical components are available in the foundry's library.
Why Can't We Just Send RTL to the Foundry? — A foundry manufactures silicon using specific transistor sizes (5nm, 7nm, 28nm…). They have a library of pre-designed, pre-tested cells (AND gates, flip-flops, buffers) called the Standard Cell Library. Your RTL code says "I want an adder" but the foundry needs to know exactly which cells to connect together, how many transistors, and what wire connections to make. Synthesis bridges this gap - it translates your behavioral intent into real, physical gate instances from the foundry's library.
Key Terms - Defined Before We Go Further
RTL (Register Transfer Level)
Verilog/VHDL code describing circuit behavior at the level of registers and data transfers. Tells you what to compute, not how to implement it in transistors. Example: assign y = a & b; is RTL for an AND gate.
Standard Cell
A pre-designed, pre-verified logic building block from the foundry library - AND2, OR3, NAND2, DFF (flip-flop), BUF, INV, MUX2. Every cell has a fixed height (fits in a row), known delay, area, and power. Synthesis maps your RTL into thousands of these cells.
Gate-Level Netlist
The output of synthesis - a file listing every standard cell instance and every wire connection between them. It's still text (Verilog), but instead of behavioral code, it says things like: AND2_X4 U101 (.A(net1), .B(net2), .Y(net3)); - a specific AND gate with specific connections.
Technology Library (.lib)
The catalog of all available cells at a specific process node and PVT condition. Contains: cell delay vs load tables, setup/hold times, leakage power, area in µm². The synthesis tool uses this to pick the right cell for each function and estimate timing. Think of it as the ingredient nutrition label.
SDC (Synopsys Design Constraints)
A file where you tell the synthesis tool your timing requirements: how fast the clock is, when data arrives at inputs, when outputs must be ready. Without SDC, synthesis has no idea what "fast enough" means and will produce a correct but potentially very slow netlist.
QoR (Quality of Results)
How good the synthesis output is, measured across multiple dimensions: timing (WNS/TNS), area (mm² or cell count), power (mW), and DRC violations. A good synthesis engineer optimizes all four simultaneously - improving one often hurts another.
Inputs to Synthesis
RTL source files (.v / .sv / .vhd) - the behavioral description Technology library (.lib / .db) - available cells and their properties SDC constraints (.sdc) - timing requirements (clock, I/O delays) UPF/CPF (optional) - low-power intent file
What Synthesis Does
1. Parses and understands your RTL code (Elaboration) 2. Converts logic to technology-independent gates (Generic Mapping) 3. Maps those to real cells from your library (Technology Mapping) 4. Optimizes: minimize delay on critical paths, reduce area, lower power (Optimization)
Outputs of Synthesis
Gate-level netlist (.v) - your RTL translated to real gates Mapped SDC (.sdc) - constraints ready for PD tool Reports - timing (WNS/TNS), area (mm²), power (mW), DRC violations DDC database - for incremental re-runs
RTL-to-GDS Complete Chip Design Flow
RTL TO GDS II DESIGN FLOW
Key Concept — Synthesis sits at the boundary of front-end and back-end design. The quality of synthesis directly impacts all downstream physical design steps - poor synthesis results in congestion, timing closure problems, and increased power.