Quality of Results (QoR)
QoR is the overall measure of synthesis success across all objectives: timing, area, power, and design rule compliance. A good synthesis engineer tracks all fou
QoR is the overall measure of synthesis success across all objectives: timing, area, power, and design rule compliance. A good synthesis engineer tracks all four simultaneously - improving one often hurts another.
Reading QoR Numbers - What Do They Mean? — After synthesis, you run report_qor and see numbers like WNS = −0.28ns, TNS = −15.4ns. Here is what that means: WNS (Worst Negative Slack) = the single worst timing path in the design. −0.28ns means the most critical path is 0.28 nanoseconds too slow - data arrives 0.28ns after it needs to. This is the path you fix first. TNS (Total Negative Slack) = the sum of all negative slacks across all violating paths. −15.4ns means if you added up all the violations, the total shortfall is 15.4ns of work to fix. A large TNS with a small WNS means many paths are slightly violated (broad problem). A large WNS with small TNS means one very bad path (focused problem). Goal: WNS ≥ 0 AND TNS = 0 - every single timing endpoint must pass. Even one path at −0.001ns is a failure at sign-off.
WNS
Worst Negative Slack
The single most critical path. Must be ≥ 0 for timing sign-off. This is what you fix first - it sets your maximum achievable frequency.
TNS
Total Negative Slack
Sum of ALL negative slacks across all endpoints. Indicates total work remaining. Must be exactly 0 at sign-off. Large TNS = many violations to fix.
WHS
Worst Hold Slack
Most critical hold violation. Hold failures happen at ALL frequencies - they are structural problems fixed with delay buffers, not by lowering frequency.
QoR Improvement Checklist
| Issue | Symptom | Fix | Priority |
|---|---|---|---|
| Setup violations | WNS < 0 | Upsize cells, remove logic levels, add pipeline stage | P0 |
| Hold violations | WHS < 0 | Insert delay buffers on short paths | P0 |
| High leakage power | report_power shows high static | Replace LVT with HVT on non-critical paths | P1 |
| High dynamic power | Switching activity high | Enable clock gating, operand isolation | P1 |
| DRC violations | Max cap/trans violations | Buffer high-fanout nets, fix transitions | P0 |
| Large area | Area > target | set_max_area 0, use higher Vt cells | P2 |