Module 35 min
Synopsys Design Compiler (DC)
Design Compiler is the industry-standard synthesis tool from Synopsys. It supports hierarchical synthesis, compile strategies, and advanced optimization for tim
Design Compiler is the industry-standard synthesis tool from Synopsys. It supports hierarchical synthesis, compile strategies, and advanced optimization for timing, area, and power.
Key DC Commands
| Command | Purpose | Key Options |
|---|---|---|
| read_verilog | Read RTL source files | -sv (SystemVerilog), file list |
| elaborate | Build design hierarchy | -parameters, -lib_work |
| link | Resolve all design references | Must be called after elaborate |
| compile_ultra | Full compile with all optimizations | -no_autoungroup, -timing_high_effort |
| compile | Basic compile | -map_effort [low/med/high], -incremental |
| report_timing | Timing path reports | -max_paths N, -slack_lesser_than 0 |
| report_area | Area statistics | -hier (hierarchical breakdown) |
| report_power | Power analysis | -analysis_effort high |
| write_file | Output gate-level netlist | -format verilog -hierarchy -output |
| write_sdc | Write constraints file | -version 2.0 |
| set_dont_touch | Protect cells from optimization | Apply to specific instances |
| check_timing | Validate timing constraints | Reports unconstrained paths |
Sample DC Synthesis Script (.tcl)
TCL - DC Synthesis Script
## =========================================================
## DC Synthesis Script - sample_chip.tcl
## Project: sample_chip | Author: VLSI Engineer
## =========================================================
## 1. Setup target/link libraries
set target_library "saed32nm_tt1p05v25c.db"
set link_library "* $target_library"
set symbol_library "saed32nm.sdb"
## 2. Read RTL sources
read_verilog -sv "../rtl/top.v ../rtl/core.v ../rtl/alu.v"
## 3. Elaborate and link design
elaborate sample_chip
link
check_design
## 4. Apply timing constraints
read_sdc "../constraints/sample_chip.sdc"
## 5. Set operating conditions
set_operating_conditions "tt1p05v25c"
## 6. Compile with high effort
compile_ultra -no_autoungroup -timing_high_effort_script
## 7. Reports
report_timing -max_paths 10 -slack_lesser_than 0 -nosplit > rpt/timing.rpt
report_area -hier > rpt/area.rpt
report_power -analysis_effort high > rpt/power.rpt
report_qor > rpt/qor.rpt
## 8. Write outputs
write_file -format verilog -hierarchy -output "out/sample_chip_netlist.v"
write_sdc -version 2.0 "out/sample_chip_mapped.sdc"
write_file -format ddc -hierarchy -output "out/sample_chip.ddc"
puts "=== Synthesis Complete ==="Sample SDC Constraint File
SDC - Timing Constraints
## =========================================================
## SDC Constraint File - sample_chip.sdc
## =========================================================
## Clock definition
create_clock -name CLK -period 5.0 -waveform {0 2.5} [get_ports clk]
## Clock uncertainty (jitter + skew)
set_clock_uncertainty -setup 0.15 [get_clocks CLK]
set_clock_uncertainty -hold 0.05 [get_clocks CLK]
## Clock transition
set_clock_transition 0.1 [get_clocks CLK]
## Input delays (relative to CLK edge)
set_input_delay -max 1.5 -clock CLK [get_ports data_in*]
set_input_delay -min 0.2 -clock CLK [get_ports data_in*]
## Output delays
set_output_delay -max 1.2 -clock CLK [get_ports data_out*]
set_output_delay -min 0.1 -clock CLK [get_ports data_out*]
## Drive strength and load
set_driving_cell -lib_cell BUFX4 [get_ports data_in*]
set_load 0.05 [get_ports data_out*]
## False paths (async reset, test ports)
set_false_path -from [get_ports rst_n]
set_false_path -from [get_ports scan_en]
## Multicycle path (2-cycle computation)
set_multicycle_path 2 -setup -from [get_cells mult_inst*]
set_multicycle_path 1 -hold -from [get_cells mult_inst*]
## Max capacitance / transition constraints
set_max_capacitance 0.2 [current_design]
set_max_transition 0.4 [current_design]