Timing Constraints (SDC)
Clock & I/O Timing Waveform - SDC Constraints Visualized
Clock & I/O Timing Waveform - SDC Constraints Visualized
This diagram shows the complete setup timing budget for a register-to-register path through an I/O port. All SDC constraint values map directly to regions on the waveform. The available combinational logic window = Period − input_delay − output_delay − setup_margin.
Input Delay Explained — set_input_delay -max 1.5 -clock CLK [get_ports data_in*] This tells the tool: upstream logic takes 1.5 ns of the clock period before data is valid at our input port. This is NOT a constraint we impose - it's a description of the external world. The tool uses it to compute the remaining time budget for our internal combinational logic. Tighter input delay = less margin for your combo path.
Output Delay Explained — set_output_delay -max 1.2 -clock CLK [get_ports data_out*] This says: the downstream chip needs our output to be valid 1.2 ns before its capture clock edge. The tool reserves this time from the end of the period. Together: available combo window = Period − input_delay − output_delay = 5.0 − 1.5 − 1.2 = 2.3 ns (before accounting for FF setup time and uncertainty).
Complete SDC Command Reference
| SDC Command | Analysis Type | What It Models | Example |
|---|---|---|---|
| create_clock | Both | Defines clock signal: period, waveform shape, source pin. Foundation of all timing analysis. | create_clock -period 5 -waveform {0 2.5} [get_ports clk] |
| create_generated_clock | Both | Clock derived from master clock (PLL output, divider). Must be declared for STA to analyze crossing paths. | create_generated_clock -divide_by 2 -source clk [get_pins div_reg/Q] |
| set_clock_uncertainty | Both | Models jitter + skew + margin. Setup reduces required time. Hold adds to minimum required time. | set_clock_uncertainty -setup 0.15 -hold 0.05 [get_clocks CLK] |
| set_clock_transition | Both | Models clock rise/fall slew at the source. Affects clock cell delays in tree analysis. | set_clock_transition 0.08 [get_clocks CLK] |
| set_input_delay -max | Setup | Latest external data arrival relative to clock. Reduces time budget for internal combo logic. | set_input_delay -max 1.5 -clock CLK [get_ports din*] |
| set_input_delay -min | Hold | Earliest external data arrival. Used for hold analysis. Without -min, hold on input paths is unconstrained. | set_input_delay -min 0.2 -clock CLK [get_ports din*] |
| set_output_delay -max | Setup | Time before next clock edge downstream chip needs our output stable. Eats into our combo budget. | set_output_delay -max 1.2 -clock CLK [get_ports dout*] |
| set_output_delay -min | Hold | Minimum time downstream chip needs output stable after our clock. Constrains minimum combo path. | set_output_delay -min 0.1 -clock CLK [get_ports dout*] |
| set_false_path | Disable | Removes path from STA entirely. For async resets, test ports, clock MUX select pins - paths never race functionally. | set_false_path -from [get_ports rst_n] |
| set_multicycle_path | Both | Allows N-cycle propagation. ALWAYS pair setup with hold correction (N-1). Missing hold fix → hold violations. | set_multicycle_path 2 -setup -from [get_cells mul*] set_multicycle_path 1 -hold -from [get_cells mul*] |
| set_clock_groups | Async | Tells STA not to analyze paths between unrelated clocks. Essential for correct CDC handling in STA. | set_clock_groups -asynchronous -group {CLK_A} -group {CLK_B} |
| set_driving_cell | Setup | Models external driver strength at input ports. Without this, input transitions are ideal (zero-resistance). Affects input timing accuracy. | set_driving_cell -lib_cell BUFX4 [get_ports din*] |
| set_load | Setup | Models output port capacitive load (downstream PCB trace, other chip input). Affects output transition and delay. | set_load 0.05 [get_ports dout*] |
Pro Tip - Pre-CTS vs Post-CTS Uncertainty — Pre-CTS: Use set_clock_uncertainty -setup 0.15 to model total skew + jitter. This is pessimistic because skew is unknown. Post-CTS: Switch to set_propagated_clock [all_clocks] in PrimeTime. The tool computes actual clock latencies through the synthesized clock tree. Only jitter uncertainty remains (typically 0.05–0.08 ns). This recovers significant timing margin - often 100–200 ps - that was previously modeled as skew pessimism.