Optimization Techniques
Trading timing, area and power across the three optimization passes: restructuring, sizing, buffering, cloning, resource sharing, clock gating, multi-Vt and DRC fixing.
Every synthesis run is optimising three things that pull against each other: timing (make it fast enough), area (make it small), and power (make it cool and efficient). You cannot maximise all three at once, a faster path usually means bigger cells (more area, more power), and a smaller design usually means slower. Optimisation is the art of spending your effort where it matters and settling the rest. Effort levels (medium/high) tell the tool how hard to push before it stops.
The QoR triangle
Quality of Results (QoR) is measured on timing, area and power together. Constrain only timing and the tool will happily burn area and power to hit it; constrain area too hard and timing suffers. Good constraints describe what you actually need, the real clock period, real I/O budgets, real max-transition rules, so the optimiser trades sensibly instead of chasing goals you do not care about.
When optimization happens
Optimisation is not one step, it runs three times, on different representations. Before mapping, the tool optimises the technology-independent boolean logic (sharing, restructuring, constant propagation). During mapping, it picks the best library cell for each function. After mapping, with real delays known, it does incremental fixes: sizing, buffering, cloning and restructuring. Understanding which pass you are in tells you which knob will actually help.
Timing optimization
Timing optimisation attacks the paths with negative slack. The tool restructures the critical path to cut logic depth (fewer gates between flops), upsizes the cells on it for more drive, inserts buffers to handle heavy loads and long nets, and clones or duplicates a cell whose output fans out to too many loads so each copy drives fewer. It swaps commutative pins so the late-arriving signal takes the fastest route, and you can weight or group critical paths so the tool spends its effort there. Retiming, moving registers across combinational logic to balance stages, is the heavier hammer when restructuring is not enough.
Area optimization
Area optimisation shrinks the design without breaking timing. It shares resources (one adder reused instead of two where the schedule allows), folds constants and removes dead and duplicate logic, downsizes cells on paths that have slack to spare, and re-maps sub-circuits to smaller cell combinations. Because it only touches slack-positive logic, area recovery is usually done after timing is met, not before.
Power optimization
Power splits into dynamic (switching) and leakage (static). The big dynamic win is clock gating, inserting integrated clock-gating cells so registers that are not changing do not toggle their clock, plus operand isolation, which stops datapath inputs from switching when their result is unused. Leakage is attacked with multi-threshold voltage: high-Vt cells leak little but switch slowly, low-Vt cells are fast but leaky, so the tool puts HVT on paths with slack and reserves LVT for the truly critical ones. Feeding real switching activity (a SAIF file) lets the tool optimise power where the design actually toggles.
Design-rule (DRC) fixing
Some limits are not optional. Maximum transition, maximum capacitance and maximum fanout are electrical legality rules the netlist must satisfy no matter what the timing looks like, a signal with too slow an edge or too many loads is simply not a valid design. The tool fixes these first, by buffering, upsizing drivers and splitting fanout, and only then optimises timing on top of a legal netlist.
Multi-Vt strategy in one picture
Threshold voltage is the main leakage-vs-speed dial. A practical flow synthesises with a leakage-friendly mix, then lets timing optimisation pull specific critical cells down to lower Vt only where they are needed. The goal is a design that is mostly high-Vt (low leakage) with just enough low-Vt cells to close timing.
| Technique | What it does | Primary benefit |
|---|---|---|
| Restructuring / retiming | Cuts logic depth on the critical path | Timing |
| Cell sizing (up / down) | More drive on critical cells, less on slack cells | Timing / area / power |
| Buffer insertion | Drives heavy loads and long nets | Timing / DRC |
| Cloning / logic duplication | Splits high fanout across copies | Timing |
| Resource sharing | Reuses one datapath unit for several ops | Area |
| Clock gating | Stops the clock to idle registers | Dynamic power |
| Multi-Vt swap | HVT on slack paths, LVT on critical paths | Leakage power |
Over-constraining is a real trap: an artificially tight clock or padded I/O delays make the tool over-size and over-buffer everywhere, bloating area and power for slack you will never use, and it hides which paths are genuinely critical. Constrain to what the design truly needs, then tighten selectively.
Recap: synthesis optimisation trades timing, area and power across three passes (pre-map logic, mapping, post-map incremental). Fix DRC legality first, close timing by cutting depth and sizing/buffering the critical paths, then recover area and power on the paths that have slack, using clock gating and multi-Vt for power. Constrain honestly so the tool optimises for what you actually need.