Power-Aware Synthesis: Clock Gating and Multi-Vt
Cutting dynamic power with gating and leakage with cell swaps
Modern synthesis does not just hit timing and area, it manages power as a first-class goal. Dynamic power is burned when nodes switch, scaling with activity, capacitance, and the square of voltage; leakage power is burned continuously as long as the cell is powered, even when nothing toggles. Two synthesis techniques attack these separately: clock gating cuts dynamic power, multi-Vt cell selection cuts leakage. They are largely independent, which is why a good flow uses both.
Clock gating insertion
A register bank with an enable normally recirculates its own value through a feedback mux every cycle, so the flops and the clock net toggle even when the data does not change. Clock gating replaces that with an integrated clock-gating cell (ICG) that shuts off the clock to the bank when the enable is low. That stops the flop clock pins and the local clock tree from switching, which is often the single largest dynamic-power saving in the design.
// RTL the tool recognizes as a gating candidate:
// always @(posedge clk) if (en) data_q <= data_d;
// Synthesis replaces the enable-mux feedback with an ICG that
// gates 'clk' to the whole bank when 'en' is low.
# Design Compiler: insert latch-based clock gating, only where
# the bank is wide enough to pay back the ICG cost.
set_clock_gating_style -sequential_cell latch \
-minimum_bitwidth 4 \
-positive_edge_logic {integrated}
compile_ultra -gate_clockMulti-Vt leakage optimization
Foundries ship the same logical cell in several threshold-voltage flavors. A low-Vt (LVT) cell is fast but leaks a lot; a high-Vt (HVT) cell is slow but leaks very little; standard-Vt (SVT) sits in between. The tool puts fast LVT cells only on paths that need the speed and swaps everything with slack to HVT, so leakage drops sharply while timing still closes.
| Cell flavor | Speed | Leakage | Where the tool uses it |
|---|---|---|---|
| LVT (low Vt) | Fastest | Highest | Critical paths only |
| SVT (standard Vt) | Medium | Medium | General logic |
| HVT (high Vt) | Slowest | Lowest | Paths with spare slack |
in an interview, separate the two cleanly: clock gating cuts dynamic power by stopping unnecessary toggling, multi-Vt cuts leakage by moving non-critical paths to slower, lower-leakage cells. The flow targets leakage by maximizing HVT content under the timing constraint, which is why a leaky design usually means too many cells stuck on LVT.
both techniques have traps. Gating tiny banks loses, because the ICG and its enable logic cost more power and area than they save, hence the minimum-bitwidth setting. And aggressive HVT swapping can quietly create hold violations on fast paths, since slower cells shift timing; multi-Vt optimization must be balanced against both setup and hold, not just leakage.