Detailed Synthesis Flow
The synthesis flow transforms RTL into an optimized gate-level netlist through several distinct stages, each with specific goals and transformations.
The synthesis flow transforms RTL into an optimized gate-level netlist through several distinct stages, each with specific goals and transformations.
SYNTHESIS STAGE-BY-STAGE FLOW
What Happens at Each Stage — Step 1 - Elaboration: The tool reads your Verilog files and "understands" your design - like a compiler parsing code. It figures out what each module does, how they connect, and what kind of logic is needed (registers, adders, FSMs). Step 2 - Generic Mapping: Converts your design into a technology-independent intermediate form using GTECH (generic) gates - simple AND/OR/NOT/FF operations with no size or speed information yet. Boolean optimization happens here: constant propagation, dead code removal, logic simplification. Step 3 - Technology Mapping: Now the tool looks at your target library (.lib file) and replaces each generic gate with an actual physical cell from that library. An AND2 becomes AND2_X4 (4x drive strength), a flip-flop becomes DFF_X1. This is where cell selection decisions are made. Step 4 - Optimization: Iteratively improve the design. Fix timing violations by upsizing cells or restructuring logic. Reduce area by downsizing non-critical cells. Insert clock gating to save power. This phase runs many passes until WNS/TNS meets your target.
Elaboration
Parses HDL source files, resolves module hierarchy, identifies registers, FSMs, and datapath elements. Builds an internal design representation (GTECH netlist) using generic logic cells independent of technology.
Technology Mapping
Maps GTECH gates to cells from the target technology library (.lib). Uses pattern matching and tree-covering algorithms to find optimal cell selections that meet timing and area targets.