Static Timing Analysis
STA is how you prove a chip will run at speed without simulating every input. This path builds your timing intuition from the ground up: setup and hold, clock definitions, uncertainty, multicycle and false paths, on-chip variation, and full signoff with PrimeTime.
Introduction to STA
What static timing analysis (STA) is and how it verifies chip timing without simulation: timing paths, setup and hold, slack, clocks, PVT corners, and where STA runs in the flow.
Timing Path Types
The four STA timing path types explained simply: register-to-register, input-to-register, register-to-output and input-to-output, with startpoints, endpoints and how each is constrained.
Setup Time, Hold Time & Slack
Setup and hold timing checks explained with equations and waveforms: what setup time and hold time are, how slack is computed, and how to fix setup vs hold violations.
Clock Domain Crossing (CDC)
Clock domain crossing in STA: why asynchronous crossings cause metastability, why STA cannot time them, the two-flop synchronizer, multi-bit bus techniques and CDC verification.
On-Chip Variation (OCV, AOCV, POCV)
On-chip variation in STA made clear: OCV flat derating, AOCV depth and distance aware derating, and POCV/SOCV statistical timing, with a worked derate example and CRPR.
Multi-Mode Multi-Corner (MMMC)
MMMC timing analysis explained: operating modes crossed with PVT corners give scenarios, why setup closes at the slow corner and hold at the fast corner, analysed concurrently.
Synopsys PrimeTime
Synopsys PrimeTime, the golden signoff STA tool: the flow (netlist, SPEF, SDC, propagated clock, report_timing), PBA, PrimeTime-SI crosstalk, ECO and distributed analysis.
Cadence Tempus
Cadence Tempus signoff STA: MMMC views, Quantus parasitics, the report_timing flow, its common flow with Innovus, signal integrity and ECO. PrimeTime’s counterpart.
Timing Closure: Fixing Setup & Hold Violations
How to fix timing violations in STA: the closure loop, speeding paths up to fix setup, adding delay to fix hold, the setup/hold trade-off, and ECO closure.
Latch Time Borrowing
Latch time borrowing (time stealing) explained: how level-sensitive latches let a slow stage borrow time from the next, the borrowing limit, a worked example, and where it is used.
CRPR / CPPR: Removing Clock Pessimism
CRPR (CPPR) explained: how OCV double-derates the common clock path, how the common-point credit removes fake pessimism, and why it matters most for hold, with a worked example.
Graph-Based vs Path-Based Analysis (GBA vs PBA)
GBA vs PBA in STA: graph-based analysis is fast but pessimistic (worst slew per node); path-based analysis re-times real paths to recover margin. When to use each, with a worked example.
Crosstalk & Signal Integrity
Crosstalk and signal integrity in STA: coupling capacitance, crosstalk delta delay (same vs opposite direction), noise glitches, fixes (spacing, shielding, NDR), and SI-aware signoff.