Multi-Mode Multi-Corner (MMMC)
MMMC timing analysis explained: operating modes crossed with PVT corners give scenarios, why setup closes at the slow corner and hold at the fast corner, analysed concurrently.
A chip has to work in more than one situation: different operating modes (running normally, in test, in standby) and across the spread of manufacturing and environment (slow vs fast silicon, high vs low voltage, hot vs cold). Multi-mode multi-corner (MMMC) analysis checks, and optimises, timing across every combination at once, so the design closes for the real world, not just one lucky case.
Modes
A mode is a set of operating constraints: which clocks are active, at what frequency, and with what exceptions. The functional mode is normal operation; test / scan mode uses a different (often slower) clock and different paths for manufacturing test; standby / low-power modes gate or slow clocks to save power. Each mode has its own SDC, and a path that is critical in one mode may be a false path in another.
Corners
A corner is a PVT + RC operating point: a process skew (slow SS, typical TT, fast FF), a supply voltage (high or low), a temperature (hot or cold), plus the RC (parasitic) extraction corner for the wires. The library (.lib) and the parasitics both change with the corner, so the same netlist has different delays at each one.
Scenarios = mode x corner
A scenario (or analysis view) is one mode paired with one corner. The full verification space is the grid of all modes crossed with all corners, and MMMC analysis covers that grid.
Which corner stresses which check
The corners are not symmetric. Setup (the long-path check) is worst at the slow corner, slow process, low voltage, and (at older nodes) high temperature, because everything is at its slowest. Hold (the short-path check) is worst at the fast corner, fast process, high voltage, low temperature, because data races through fastest. So a design must close setup at the slow corner and hold at the fast corner simultaneously, which is exactly why both must be analysed together.
Why analyse them concurrently
Fixing a violation in one scenario can create one in another, a hold buffer added for the fast corner changes setup at the slow corner. MMMC lets the tool see every scenario at once and optimise so all of them close together, instead of the whack-a-mole of fixing one corner and breaking the next. Modern flows run MMMC in synthesis, place-and-route and signoff.
| Corner | Process / V / T | Stresses |
|---|---|---|
| Slow (SS) | Slow process, low V, high T | Setup (max delay) |
| Fast (FF) | Fast process, high V, low T | Hold (min delay) |
| Typical (TT) | Nominal | Reference / power |
Recap: MMMC checks timing across every mode (functional, test, standby) crossed with every PVT corner. Setup closes at the slow corner, hold at the fast corner, and analysing them concurrently is what stops a fix in one scenario from breaking another.