Latch Time Borrowing
Latch time borrowing (time stealing) explained: how level-sensitive latches let a slow stage borrow time from the next, the borrowing limit, a worked example, and where it is used.
A flip-flop has a hard deadline: data must arrive before the clock edge, full stop. A latch is level-sensitive, it is transparent (open) for a whole phase of the clock, so data that arrives a little late, during that transparent window, still passes straight through. That flexibility is time borrowing: a slow logic stage borrows time from the next stage. It is a powerful way to average slack across stages, and a favourite interview topic.
Flip-flops vs latches
A flip-flop captures on the clock edge, a single instant, so timing is measured edge to edge. A latch captures on the clock level: while the enable is active the latch is transparent and its output follows its input; when the enable goes inactive it holds the last value. Because the capture point is a window, not an instant, a latch-based path has slack it can lend and borrow.
How time borrowing works
Suppose two latch stages are half a cycle apart. If the logic feeding the second latch is slow and its data is not ready by the nominal (edge) point, it does not immediately fail, as long as the data arrives while that latch is still transparent, it is captured. The stage has effectively borrowed the extra time from the transparent window. STA models this automatically for latch-based designs.
The borrowing limit
Borrowing is not free and not unlimited. A stage can only borrow up to the width of the next latch's transparent phase, and whatever it borrows is taken away from the time the following stage has, the borrowed time is paid back downstream. So borrowing balances a lumpy pipeline (one slow stage, one fast stage) but cannot rescue a path that is slow across every stage.
Worked example
Say each phase is 1.0 ns and a stage's logic needs 1.2 ns, 0.2 ns too much for a strict edge. With latches it borrows 0.2 ns into the next transparent phase and still captures. But the next stage now starts 0.2 ns late, so it must finish in 0.8 ns instead of 1.0. If it can, the pipeline works; if it also needs the full 1.0, the borrowing chain breaks and you have a real violation.
Where it is used, and the catch
Time borrowing (and its edge-triggered cousin, useful skew or cycle stealing) is common in high-performance and custom design to squeeze out the last of the frequency. The catch is complexity: latch-based timing is harder to analyse, harder to test, and easier to get wrong, so most standard-cell flows use flip-flops and reserve borrowing for where it truly pays. It connects directly to the setup/hold ideas in Setup, Hold & Slack.
Recap: a latch is transparent for a clock phase, so data arriving late still passes: the stage borrows time from the next latch's window. Borrowing is capped by the transparent-phase width and is repaid by the following stage, so it balances an uneven pipeline but cannot fix a uniformly slow path.