Latch Borrowing
Latch borrowing (also called time borrowing) is a timing technique where a slow logic stage borrows time from the next pipeline stage using level-sensitive latc
Latch borrowing (also called time borrowing) is a timing technique where a slow logic stage borrows time from the next pipeline stage using level-sensitive latches instead of edge-triggered flip-flops. It allows timing slack to be redistributed across pipeline stages - a stage that needs more time can take it from a stage that has extra.
Why Latches Enable Borrowing but Flip-Flops Don't — A flip-flop captures data only at the clock edge - timing budget is strictly one clock period per stage. A level-sensitive latch is transparent during the entire clock high (or low) phase - if data arrives late, it can still pass through as long as it arrives before the latch closes. This extra window = borrowed time.
Maximum Borrow Limit — A latch can borrow at most T/2 (half the clock period) - the full window when the latch is transparent. If Logic A takes more than 1.5T total (1T + T/2 borrow max), it will cause a hold violation on the next latch because data arrives after the latch closes. Max Borrow = Tclk / 2 Violated if: Data delay > Tclk + Tclk/2
When Synthesis Uses Latch Borrowing — Synthesis tools (DC, Genus) can automatically infer latch-based pipelines when directed. Use: # DC: enable retiming with latches compile_ultra -retime # Allow latch-based time borrowing set_dont_use -false [get_lib_cells *latch*]
Latch Borrowing in STA Reports
| STA Concept | Flip-Flop Behavior | Latch Behavior |
|---|---|---|
| Timing window | Strictly 1 clock period | Can borrow up to T/2 from next stage |
| Setup check | Data must arrive before clock edge | Data must arrive before latch closes (end of transparent phase) |
| Hold check | Data must hold after clock edge | Data must hold past latch opening edge (more complex) |
| Time borrowed (STA report) | Not applicable | Reported as "Time Borrowed" in PT/Tempus |
| Slack calculation | Standard slack formula | Slack = Available window − (data delay − borrowed time) |
| Tool command | report_timing | report_timing -pba_mode (PBA often needed for latches) |
Latch Borrowing Tradeoffs — Pros: Redistributes timing slack across pipeline stages without changing clock frequency. Used in high-performance CPUs (RISC-V cores, custom datapaths). Cons: Latches are harder to scan (DFT insertion is more complex). STA is more complex - hold checks on latches require careful constraint setup. CDC with latches is particularly tricky. Most digital ASIC flows prefer FFs for simplicity unless performance demands latch borrowing.
R
I had been struggling with OCV, AOCV, and CPPR for months. The STA section on SiliconPath explained the difference clearly with real numbers and examples - something no textbook ever did. I used this exact knowledge to answer the hardest timing question in my Intel interview. Cleared it first attempt.
Rahul Menon
STA Engineer · Qualcomm India, Bangalore