Introduction to STA
Key Terms - Defined Before We Go Further
Start Here - Why Does Timing Matter At All? — Every digital circuit operates on a clock - a signal that ticks millions or billions of times per second. On each tick, every flip-flop captures whatever data is at its input at that exact moment. The fundamental question STA answers is: "Does the data have enough time to travel from one flip-flop to the next between two consecutive clock ticks?" If yes → the chip works. If no → the chip captures wrong data → functional failure. STA checks this for every single one of the potentially millions of paths in your design.
Key Terms - Defined Before We Go Further
Flip-Flop (Register)
A memory element that captures (stores) its input D on the rising edge of the clock and presents it at output Q. Every register in your design is a flip-flop. Synthesis maps Verilog always @(posedge clk) blocks to flip-flop cells from the library.
Combinational Logic
Logic gates (AND, OR, NAND, MUX, adders…) between flip-flops. No memory - output depends only on current inputs. Data has to propagate through these gates within one clock period. The more gates in the path, the longer it takes, the lower the maximum frequency.
Clock Period
The time between two rising clock edges. A 1 GHz clock has period = 1ns. A 500 MHz clock has period = 2ns. All combinational logic between two FFs must finish within one period (minus setup time and clock uncertainty). The period sets your timing budget.
Timing Path
The route data travels from a starting point (a FF output or input port) through combinational gates to an ending point (a FF input or output port). STA measures the propagation delay of every timing path and checks it against the constraint.
Slack
Timing margin = Required Time − Actual Arrival Time. Positive slack (+) = data arrives early enough - timing is MET. Negative slack (−) = data arrives too late - timing VIOLATED. Goal: all slacks ≥ 0 at sign-off.
Critical Path
The timing path with the worst (most negative or least positive) slack. This is the bottleneck that limits your maximum operating frequency. Fixing the critical path is the primary goal of timing closure. WNS (Worst Negative Slack) = the slack of the critical path.
Why STA over Dynamic Simulation?
Dynamic simulation requires test vectors, is slow, and may miss rare corner-case paths. STA analyzes ALL paths statically in minutes, covering 100% of the design space including paths with near-zero functional probability. A design with 1M flip-flops has trillions of possible paths - only STA can check them all.
STA Limitations - What It Cannot Catch
STA cannot catch functional logic bugs (wrong RTL behavior), doesn't simulate dynamic power behavior, and requires correctly specified constraints (garbage-in garbage-out). False paths and multicycle paths must be explicitly declared by the engineer - STA trusts what you tell it.
Setup Time & Hold Time Waveforms