Introduction to STA

What is static timing analysis?

Static timing analysis is a vector-less method of verifying that a synchronous digital circuit meets its timing requirements. "Static" means it does not depend on the data flowing through the design, it analyses the structure of every path and the delays of the cells and wires on it, then compares the result against the timing constraints (the clock period and the setup/hold requirements). Because it checks every path rather than the handful a simulation happens to exercise, STA gives complete timing coverage.

A simple analogy: imagine you must check that every delivery in a city reaches its address before a deadline. You could send a van down each route and time it, that is simulation: slow, and you might never try the one route that misses. Or you could take the map, add up the known travel time of every road on each route, and instantly flag any route that arrives late, that is STA. It never "drives" the design with data; it adds up known delays along every path and checks them all against the clock at once.

Static vs dynamic timing analysis

Dynamic timing analysis means running a gate-level simulation with real input vectors and watching for timing failures. It is accurate for the paths the vectors happen to toggle, but on a large design it is impossibly slow and it can never guarantee it exercised the worst-case path. STA takes the opposite approach: it ignores functionality entirely and evaluates every path's delay against the clock. It is orders of magnitude faster and gives full coverage, which is exactly why signoff timing is always STA, not simulation.

The timing path and the timing model

Everything in STA is built on the timing path: it runs from a startpoint (a flip-flop clock pin or an input port) through combinational logic to an endpoint (a flip-flop data pin or an output port). STA computes the arrival time of data at the endpoint by summing the clock-to-Q delay of the launch flop plus every cell and net delay along the way, and compares it to the required time set by the clock. There are four kinds of path, see Timing Path Types.

Timing arcs: where the delay actually lives

STA gets its delay numbers from timing arcs. Every cell in the library carries arcs that describe how a change on an input reaches an output: the delay from the input switching to the output switching, and how the output transition (its slew, or edge rate) depends on the input slew and the output load. A cell delay is not one fixed number, it is a small table in the .lib looked up by input slew and output capacitance, so the same gate is faster when lightly loaded and slower when driving a lot. STA walks the arcs along a path, looks up each cell's delay for its actual conditions, and adds them up. Flip-flops also carry constraint arcs (setup and hold) that define the required window at the D pin.

Arcs also have a sense, called unateness. A positive unate arc means a rising input gives a rising output, so rise follows rise (a buffer, or an AND output with respect to one input). A negative unate arc means a rising input gives a falling output (an inverter, a NAND). A non-unate arc, like an XOR input or the clock-to-Q of a flop, can drive the output either way. Unateness tells STA which input edge produces the worst-case output edge, which is how it builds the true worst-case path.

The timing graph

Under the hood STA turns the whole netlist into a timing graph: a directed acyclic graph whose nodes are pins and whose edges are the timing arcs (through cells and along nets). It then makes two sweeps. A forward pass propagates arrival times from every startpoint, computing when a signal actually reaches each node. A backward pass propagates required times from every endpoint, computing when it must arrive. Slack at any node is simply required minus arrival. Because it is one graph traversal rather than an enumeration of every path, STA can analyse millions of paths in a single near-linear sweep, which is exactly why it scales to a whole chip while simulation cannot.

Setup and hold, the two checks on every path

Each path is checked two ways. The setup check asks whether data arrives early enough, before the next clock edge, with a setup margin to spare. The hold check asks whether data arrives late enough, that new data does not race through and corrupt the value the flop is still capturing from the previous edge. These two checks are the heart of STA; they are covered in depth in Setup Time, Hold Time & Slack.

Slack, the one number that matters

Slack is the margin on a path: slack = required time - arrival time. Positive slack means the path meets timing; negative slack means it fails. The whole design is summarised by two numbers, WNS (worst negative slack), the single most critical path, and TNS (total negative slack), the sum over all failing endpoints. Driving both to zero is the goal of timing closure.

Clocks, uncertainty and PVT corners

STA is only as good as its clock definitions and its margins. You define clocks and their I/O timing in the SDC (see Timing Constraints (SDC)), and you hold back margin for real-world imperfection with clock uncertainty (skew + jitter). Silicon also varies, so timing is checked across PVT corners (process, voltage, temperature) and with on-chip variation derating, the subjects of On-Chip Variation (OCV/AOCV) and Multi-Mode Multi-Corner (MMMC).

Where STA runs in the flow

STA is run repeatedly, on increasingly real data. After synthesis it uses an ideal clock and estimated wire loads. After clock tree synthesis it switches to the propagated (real) clock. At signoff, after routing, it uses extracted parasitics for accurate net delays and is run in a dedicated signoff tool, Synopsys PrimeTime or Cadence Tempus, across every corner and mode.

Why STA matters

STA is what lets a team commit a design to a foundry with confidence. It proves the maximum frequency, finds every setup and hold violation before silicon exists, and does it without writing a single test vector. Fluency in STA, reading a timing report, understanding slack, knowing why a path fails and how to fix it, is the single most tested skill in VLSI interviews. Practice it on our 128 STA interview questions.