Timing Path Types
The four STA timing path types explained simply: register-to-register, input-to-register, register-to-output and input-to-output, with startpoints, endpoints and how each is constrained.
Data never floats freely inside a chip. On a clock edge it is launched from one flip-flop, it travels through a few logic gates, and it must be caught by another flip-flop on the next edge. That journey, from where the data sets off to where it is caught, is one timing path. STA chops the whole chip into millions of these little journeys and checks each one against the clock. Sort them by where they begin and end and there are only four kinds, and every timing report you will ever read is written in this vocabulary.
Startpoints and endpoints
Two words unlock everything else. A startpoint is where data sets off: either the clock pin of a flip-flop (on the edge, its output Q launches new data) or a primary input port (data arrives from another chip). An endpoint is where data is caught: either the data (D) pin of a flip-flop (checked for setup and hold) or a primary output port (checked against what the next chip needs). Every single timing path runs from exactly one startpoint to exactly one endpoint, and that is the only thing that changes between the four types below.
The four timing path types
The four types come from a single question asked twice: does the path start at a flip-flop or at an input port, and does it end at a flip-flop or at an output port? Two options on each end give exactly four combinations. The diagram below shows all four on one block, the same input port, two flip-flops and one output port carry every type.
Register to register (reg2reg)
The internal core paths, launch flop to capture flop through combinational logic. These are by far the most numerous paths in a design and they are what usually set the clock frequency. Both endpoints are inside the chip, so both the launch and capture edges come from your own clock tree.
Input to register (in2reg)
From a primary input port to the data pin of a register. The startpoint is off-chip, so STA cannot see the upstream logic, you describe its arrival with set_input_delay in the SDC. The path is: external arrival, then your input logic, checked against the capture flop's setup and hold.
Register to output (reg2out)
From a register out to a primary output port. The endpoint is off-chip, so you tell STA how much time the downstream chip needs with set_output_delay. The path is: launch flop, then your output logic, and it must be valid before the downstream device's own capture edge.
Input to output (in2out)
A pure combinational feedthrough, from an input port straight to an output port with no register in between. Both ends are off-chip, so the path is bounded by both input and output delay. These are less common but easy to forget to constrain, which leaves them unchecked.
Path groups and how STA reports them
STA sorts paths into path groups (usually by the capture clock, plus special groups for I/O and async paths) and reports the worst paths per group. report_timing walks a path and prints the arrival and required times stage by stage, this is the report you learn to read fluently. Every one of the four types is analysed for both the setup (max) and hold (min) checks covered in Setup, Hold & Slack.
| Path type | Startpoint | Endpoint | Constrained by |
|---|---|---|---|
| reg to reg | FF clock pin | FF data pin | Clock period (internal) |
| in to reg | Input port | FF data pin | set_input_delay |
| reg to out | FF clock pin | Output port | set_output_delay |
| in to out | Input port | Output port | input + output delay |
Recap: four path types: reg-to-reg (internal, sets frequency), in-to-reg (bounded by input delay), reg-to-out (bounded by output delay), and in-to-out (combinational feedthrough). Each runs startpoint to endpoint and is checked for setup and hold. Miss a constraint on the boundary paths and they silently go unchecked.