Module 91 min
Timing Closure Techniques
Fixing Setup Violations
Fixing Setup Violations
| Technique | Method |
|---|---|
| Cell Upsizing | Replace slow cell with larger drive strength version (X4 → X8) |
| Buffer Insertion | Split long wire into shorter segments with buffers |
| Logic Restructuring | Reduce logic depth on critical path by rearranging gate tree |
| Floorplan Change | Move source/sink cells closer to reduce wire delay |
| Retiming | Move registers to balance pipeline stages |
| Frequency Reduction | Last resort: lower clock frequency (increase period) |
Fixing Hold Violations
| Technique | Method |
|---|---|
| Buffer Insertion | Insert delay buffers (delay cells) on short paths to add delay |
| Cell Downsizing | Replace fast (LVT) cell with slower (HVT) version |
| Wire Stretching | Make path wire longer to add RC delay |
| Clock Skewing | Intentionally skew clock to give more hold margin |
ECO (Engineering Change Order) Flow
Pro Tip
What is ECO? — ECO is a controlled method to make targeted netlist changes after synthesis or tape-out to fix timing, functional bugs, or sign-off issues. It modifies only the affected cells/nets, preserving the rest of the design.