Timing Closure: Fixing Setup & Hold Violations
How to fix timing violations in STA: the closure loop, speeding paths up to fix setup, adding delay to fix hold, the setup/hold trade-off, and ECO closure.
Timing closure is the process of driving every path's slack to zero or positive across all corners. It is a loop: analyse, find the violations, fix them, re-check, and repeat until WNS and TNS are clean. The trick is that setup and hold want opposite things, so you fix them in opposite directions and constantly re-check that fixing one did not break the other.
The timing closure loop
You run STA, read the worst paths, apply targeted fixes, and re-run. Early in the flow the tool does most of this automatically during placement and CTS optimisation; late in the flow you close the last violations with precise, incremental ECOs so you do not disturb paths that are already clean. Closure is done when every scenario shows WNS ≥ 0 with the required margin.
Fixing setup violations (make the path faster)
A setup violation means the data path is too slow, so every fix makes data arrive earlier:
- Restructure / reduce logic depth, fewer levels of gates between the flops (the biggest lever).
- Upsize the critical cells, more drive strength shortens their delay.
- Buffer long or heavily-loaded nets so they drive cleanly.
- Use LVT cells on the critical path (faster, at the cost of leakage).
- Apply useful skew, delay the capture clock a little to lend the path time.
- Retime, move a register across logic to balance the stages.
- Improve placement so connected cells sit closer (shorter wires).
Fixing hold violations (make the path slower)
A hold violation means data races through too fast, so the fixes add delay:
- Insert delay / hold buffers on the short path, the standard, automated hold fix.
- Downsize or swap the fast cells to slower (higher-Vt) versions.
- Rebalance clock skew so the capture edge is not too early relative to launch.
The setup / hold trade-off
Because the fixes are opposite, they interact: speeding a path up to close setup can open a hold violation on the same or a neighbouring path, and the delay you add for hold eats setup margin. Tools fix hold after setup for this reason, and re-check setup afterwards. Fix in the right order and re-verify, never fix blindly. The full setup/hold mechanics are in Setup, Hold & Slack.
ECO closure
Late fixes are done as ECOs (engineering change orders): the tool changes only the cells on the violating paths and re-routes just those nets, leaving the rest of the design untouched. Signoff STA in PrimeTime or Tempus generates the ECO, which is then implemented incrementally in place-and-route.
| Violation | Direction | Typical fixes |
|---|---|---|
| Setup (path too slow) | Make faster | Restructure, upsize, buffer, LVT, useful skew, retime |
| Hold (path too fast) | Make slower | Delay/hold buffers, downsize, HVT, skew rebalance |
| DRC (max tran/cap/fanout) | Fix legality first | Buffer, upsize, split fanout |
Do not over-fix. Padding constraints or over-buffering to chase margin you do not need bloats area and power and can hide the real critical path. Close to the target with margin, verify across all corners, and stop.
Recap: timing closure is the analyse-fix-recheck loop. Fix setup by speeding the path up (restructure, upsize, useful skew); fix hold by slowing it down (delay buffers). They pull against each other, so fix in order and always re-verify, and finish the last violations with incremental ECOs.