On-Chip Variation (OCV) & AOCV
Real silicon has spatial and temporal variation in process, voltage, and temperature (PVT). OCV models capture that cells on the same die can behave differently
Real silicon has spatial and temporal variation in process, voltage, and temperature (PVT). OCV models capture that cells on the same die can behave differently from each other.
Process Corners
FF - Fast NMOS, Fast PMOS. Cells are fast. Best-case for timing.
TT - Typical-Typical. Nominal design point.
SS - Slow NMOS, Slow PMOS. Worst-case for setup timing.
Voltage & Temperature
Low voltage + high temp = slow cells (worst setup). High voltage + low temp = fast cells (worst hold). Temperature inversion: at advanced nodes (<65nm) speed increases with temperature in some conditions.
Derating
Apply derating factors to account for OCV. Late (slow) path: multiply by 1.05 (5% slower). Early (fast) path: multiply by 0.95 (5% faster). Creates pessimistic timing margin.
| Method | Description | Accuracy | Pessimism |
|---|---|---|---|
| OCV (flat derating) | Apply fixed derate to all paths equally | Medium | High |
| AOCV (Advanced) | Derate based on depth (number of cells in path). Longer paths have more statistical averaging → less pessimism | High | Medium |
| POCV (Parametric) | Full statistical model using σ distributions for each cell. Most accurate | Highest | Low |