Physical Verification
Before a design tapes out it has to pass physical verification. This path covers Design Rule Checking, Layout Versus Schematic, antenna and ERC checks. You learn what each check is protecting against, how to read violation reports, and how to fix the common ones without breaking timing.
Overview
Checks that every wire, via, and shape meets the foundry's minimum size and spacing rules. Violations mean the photolithography process cannot print your shapes
PV Flow Overview
Physical Verification consists of several distinct checks, each targeting a different failure mode. They must all be run at sign-off, typically in this order:
DRC - Design Rule Check
DRC verifies that your layout geometry satisfies every manufacturing rule in the foundry's PDK. These rules exist because the lithography and etching processes
LVS - Layout vs. Schematic
LVS extracts a netlist from your physical layout (by tracing metal connectivity and identifying transistors) and compares it against your reference schematic/ne
ERC - Electrical Rule Check
ERC catches electrical issues that DRC and LVS miss. A layout can be DRC-clean and LVS-clean but still have electrical errors that cause chip malfunction.
Antenna Check
During plasma etching in fabrication, metal connected to gate terminals accumulates charge. The antenna ratio is the cumulative metal area divided by the gate a
Metal Fill & Density Rules
CMP (Chemical Mechanical Polishing) planarizes each metal layer. Non-uniform metal density causes uneven polishing: sparse areas "dish" (metal removed excessive
PV Tool Knowledge
Calibre from Siemens EDA (formerly Mentor Graphics) is the industry-standard sign-off verification tool. Virtually all foundry PDKs are certified for Calibre. I
Physical Verification - Interview Questions
DRC (Design Rule Check): Checks layout geometry against foundry manufacturing rules - spacing, width, enclosure. Ensures the chip CAN be manufactured.