Module 43 min

LVS - Layout vs. Schematic

LVS extracts a netlist from your physical layout (by tracing metal connectivity and identifying transistors) and compares it against your reference schematic/ne

LVS extracts a netlist from your physical layout (by tracing metal connectivity and identifying transistors) and compares it against your reference schematic/netlist. Any mismatch is a critical bug that would cause chip failure.

How LVS Works - Step by Step

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Common LVS Error Types and Root Causes

LVS Error	What It Means	Root Cause	How to Debug
Open Net	A connection present in the schematic is missing in the layout - net is broken	Missing wire segment, broken via, net not routed, missing metal fill connection	Highlight the net in layout viewer. Find the discontinuity. Add missing wire/via segment.
Short Circuit	Two nets that should be separate are electrically connected in layout	Routing DRC waiver created a short, accidentally connected polygons, missing wire cut	Identify which two nets are shorted. Find where they touch. Remove the connection or add a cut.
Device Mismatch	Device exists in schematic but not in layout (or vice versa)	Cell not placed, wrong cell reference, flatten/unflatten issue, macro not properly instantiated	Compare instance counts. Find missing instance in layout. Check hierarchy mapping.
Port Mismatch	Port name or type doesn't match between layout and schematic	Wrong pin label on layout port, renaming in synthesis not propagated to layout, case mismatch	Check label text on layout pins vs netlist port names. Calibre is case-sensitive.
Unconnected Port	A port declared in the netlist has no connection in the layout	I/O pad not connected to core, power domain port not properly tied, spare gate left floating	Find the port in the layout. Verify it has a metal label and is connected to the correct net.
Parameter Mismatch	Device dimensions differ between layout and schematic (W/L, capacitor value)	Standard cell used wrong size, analog cell manually edited without updating schematic	Check transistor W/L in layout vs SPICE netlist. Typically only affects analog blocks.

SHELL - Calibre LVS Run + Key Report Fields

# Calibre LVS run
calibre -lvs \
    -hier \
    -turbo 16 \
    -64 \
    -runset    ./lvs_runset.svrf \
    -gds       ./out/chip_final.gds \
    -top       chip_top \
    -netlist   ./out/chip_netlist.v  # reference from synthesis

# LVS report sections to check:
# 1. CIRCUIT COMPARISON RESULTS  -  Overall PASS/FAIL
# 2. SHORTS  -  nets merged that shouldn't be
# 3. OPENS  -  nets split that should be connected
# 4. UNMATCHED NETS  -  present in one side only
# 5. UNMATCHED INSTANCES  -  devices missing

# LVS clean confirmation in report:
# "CORRECT" → clean
# "INCORRECT" → failures exist

# Quick grep for errors:
grep -E "INCORRECT|SHORTS|OPENS|Unmatched" lvs_summary.rep