Module 72 min
Metal Fill & Density Rules
CMP (Chemical Mechanical Polishing) planarizes each metal layer. Non-uniform metal density causes uneven polishing: sparse areas "dish" (metal removed excessive
CMP (Chemical Mechanical Polishing) planarizes each metal layer. Non-uniform metal density causes uneven polishing: sparse areas "dish" (metal removed excessively) and dense areas retain more. Both cause via formation failures and reliability issues.
| Parameter | Typical Range | Effect of Violation |
|---|---|---|
| Minimum metal density | 20–30% per check window | Dishing: metal recedes below ILD surface → via misses metal → open circuit |
| Maximum metal density | 70–80% per check window | Erosion: ILD polished away → shorts between layers, increased leakage |
| Check window size | 50×50 µm – 200×200 µm | Foundry-defined. Smaller windows = tighter local control |
| Fill shape min size | ≥ Wmin per layer | Too-small fill shapes violate width rules themselves |
| Fill to signal spacing | ≥ 2× normal spacing | Fill too close to signal → coupling capacitance → SI issues |
SHELL - Calibre Metal Fill Insertion
# Run Calibre fill (after routing, before final DRC)
calibre -drc -hier -runset fill_runset.svrf
# fill_runset.svrf key options:
LAYOUT SYSTEM GDSII
LAYOUT PATH "chip_prefill.gds"
DRC RESULTS DATABASE "fill_out.gds" ; GDS with fill added
# Fill insertion is non-electrical - it must NOT connect to any signal net
# Most foundry fill decks insert floating unconnected metal polygons
# Some advanced PDKs insert connected fill for better SI (optional)
# After fill: re-run DRC to verify:
# 1. Fill shapes themselves don't create new DRC violations
# 2. Fill-to-signal spacing rules satisfied
# 3. Density targets met on all layers