Overview
Checks that every wire, via, and shape meets the foundry's minimum size and spacing rules. Violations mean the photolithography process cannot print your shapes
Start Here - What Is Physical Verification? — After Physical Design completes, you have a GDS II file - the full geometric layout of your chip. But how do you know it's actually manufacturable? That it matches your circuit? That it won't destroy itself electrically? Physical Verification is the set of automated checks that answer all these questions before sending the GDS to the foundry. Think of it as the final quality inspection before manufacturing. A single unresolved DRC violation → foundry rejects your file. A single LVS open → chip has a broken wire → dead chip. PV sign-off is non-negotiable.
DRC - Will the foundry be able to manufacture it?
Checks that every wire, via, and shape meets the foundry's minimum size and spacing rules. Violations mean the photolithography process cannot print your shapes correctly → defective chip.
LVS - Does the layout match the netlist?
Extracts the connectivity from your physical layout and compares it to the reference netlist. A mismatch means a wire is missing, shorted, or connected to the wrong place → wrong circuit manufactured.
ERC / Antenna - Will it work electrically?
Checks for floating gates, ESD risks, latchup, and plasma damage to gate oxide. DRC-clean + LVS-clean is not enough - ERC violations can destroy the chip during manufacturing or use.
Why PV Is Critical - The Stakes — Unlike simulation (checks function) or STA (checks timing), Physical Verification checks manufacturability and physical correctness. A chip that simulates perfectly and passes STA but has a spacing DRC violation will either fail in the fab or be rejected at tape-out review. A modern chip tapeout costs $500K–$5M for the mask set. One missed LVS open = wasted silicon run = millions of dollars lost. PV is the last line of defense.