Module 51 min
ERC - Electrical Rule Check
ERC catches electrical issues that DRC and LVS miss. A layout can be DRC-clean and LVS-clean but still have electrical errors that cause chip malfunction.
ERC catches electrical issues that DRC and LVS miss. A layout can be DRC-clean and LVS-clean but still have electrical errors that cause chip malfunction.
| ERC Check | What It Detects | Consequence if Missed |
|---|---|---|
| Floating Gate | MOSFET gate connected to nothing (floating net) | Gate floats to indeterminate voltage → random switching behavior. Very common ERC error in early PD. |
| Floating Well | N-well or P-well not connected to VDD/VSS | Well floats → transistors biased incorrectly → latchup risk, parametric failures |
| VDD/VSS Short | Power and ground nets connected together | Direct short circuit → chip draws excessive current → burns out immediately on power-up |
| Input Not Driven | Logic input pin with no driver | Input floats → oscillation, metastability, excessive power consumption |
| Output Contention | Two outputs driving the same net simultaneously | Short circuit between drivers → device damage, incorrect logic level |
| ESD Violation | I/O pad has insufficient ESD protection structure | ESD event during handling destroys input gate oxide → dead chip before it even runs |
| Latchup Violation | Tap cells too far from active region (>50µm) | Parasitic SCR triggers → VDD-to-VSS latchup → chip permanently damaged |