Physical Verification - Interview Questions

1. What is the difference between DRC, LVS, and ERC? Which must pass for tape-out?

DRC (Design Rule Check): Checks layout geometry against foundry manufacturing rules - spacing, width, enclosure. Ensures the chip CAN be manufactured.

LVS (Layout vs Schematic): Extracts connectivity from layout and compares to reference netlist. Ensures the manufactured chip WILL match the intended circuit.

ERC (Electrical Rule Check): Checks for floating nodes, power/ground violations, ESD issues. Ensures the chip WILL WORK electrically.

All three must be 100% clean for tape-out. No exceptions. A single unresolved error means the foundry rejects the submission or the chip is at risk.

2. What is an antenna violation and how do you fix it?

An antenna violation occurs when the ratio of metal area connected to a gate terminal exceeds the foundry's limit during plasma etching. The metal accumulates charge which can tunnel through and damage the gate oxide - permanently destroying the transistor.

Two fixes:

• Layer jump: Route the wire through a higher metal layer before connecting to the gate. Higher layers are deposited later → less plasma exposure time → less charge accumulation. This is the preferred fix as it adds no area.

• Antenna diode: Insert a reverse-biased diode (anode on the net, cathode to VSS) at the gate input. During fab, accumulated charge safely bleeds to ground through the diode. Adds small area (~0.5–1 std cell)

3. What causes an LVS short and how do you debug it?

An LVS short means two nets that should be electrically separate in the schematic are connected in the layout.

Common causes:

• Two wires on the same metal layer touching (spacing DRC violation that was waived)

• Via connecting two unrelated nets through the same via hole

• Accidentally connected power/signal during manual ECO

• Missing via cut between two nets running over each other

Debug: Open Calibre RVE. Click the shorted net pair. The tool highlights in layout. Zoom to find the touching shapes. Check the DRC results - usually there's a spacing violation co-located with the LVS short. Fix the spacing violation to separate the nets.

4. What is a DRC waiver and when is it appropriate?

A DRC waiver is an explicit exception that suppresses a specific DRC violation from being reported, with foundry documentation justifying why it's acceptable.

Legitimate use cases:

• Spacing violations in ESD clamp cells - intentionally tight by design, foundry-approved cell

• Density violations in seal ring or pad ring areas - these regions have special rules

• Known violations inside foundry-provided hard IP (black box) - foundry-guaranteed correct

Never waive: Violations you don't understand. Violations in custom logic you designed. Always document the waiver with justification and get foundry approval if required. Incorrect waivers = chip failure in fab.

5. Why does metal fill affect timing, and how do you manage it?

Metal fill polygons are floating (unconnected) metal shapes on each layer. Although electrically disconnected, they add parasitic coupling capacitance to nearby signal wires. This:

• Increases wire capacitance → slower transitions → increased propagation delay

• Adds coupling between fill and signal → minor crosstalk noise

• Can shift timing by 2–5% on metal-dense designs

Management:

• Run fill insertion BEFORE final sign-off STA (not after). STA must include fill parasitics.

• Foundry fill rules specify minimum fill-to-signal spacing - this limits coupling impact.

• Some flows use "timing-aware fill" which avoids placing fill near critical nets.

• StarRC/Calibre xRC re-extraction after fill captures the additional capacitance in SPEF.

6. What is double patterning and which nodes require it?

Double Patterning (DP) splits a single metal layer's patterns into two separate photomasks that are exposed sequentially. After first exposure + etch, the second mask fills in the remaining patterns. Together they achieve pitches half of what single exposure can print.

Required at:

• 28nm: some critical layers

• 20nm/16nm: M1, M2, via layers

• 10nm/7nm: Most metal layers, Fin definition, contact layers

DRC implications: Adjacent wires on a DP layer must be "colorable" - assigned to alternating masks without conflict. A "coloring conflict" occurs when three adjacent wires are too close together to assign alternating colors without two same-color wires violating spacing. Requires routing perturbation to resolve.

7. What is Calibre xRC and how does it relate to STA sign-off?

Calibre xRC (eXtracted RC) is Calibre's parasitic extraction engine. It reads the post-route GDS layout and computes the actual resistance (R) and capacitance (C) of every metal wire and via, outputting a SPEF file.

Relationship to STA:

• Routing completes → GDS generated

• Calibre xRC reads GDS → produces chip.spef

• PrimeTime reads chip.spef via read_parasitics

• Wire delays computed from real RC → accurate back-annotated timing

• Sign-off STA with real parasitics must pass before tape-out

Pre-route timing uses estimated loads (WLM) which can be 20–40% off. Calibre xRC gives ground-truth parasitic data within ~3% of silicon silicon measurement. Without SPEF from Calibre xRC, timing sign-off is not reliable.

8. How do you approach a large DRC run with 50,000 violations?

50,000 violations sounds overwhelming but they're usually from just 3–5 root causes. Systematic approach:

• Sort by rule, count descending: grep "RULE" drc_summary.rpt | sort -k3 -rn. The top rule might account for 40,000 violations from one root cause.

• Fix the top rule first: Understand why it's occurring. Is it a routing configuration issue? A macro halo not set? A missing fill constraint?

• Batch fix vs point fix: If 10,000 violations are "M2 spacing" due to track pitch, fix the router configuration and re-route - don't fix them one by one.

• Re-run DRC after each major fix: Cascade effects - fixing spacing might introduce new width violations.

• Isolate by region: If violations cluster in one area, focus there. Use Calibre's "check window" to run DRC on a sub-region during debug.

9. What is LVS clean vs LVS correct - is there a difference?

LVS clean: Calibre reports "CORRECT" - all nodes match between layout and schematic. No shorts, opens, or device mismatches. This is what tape-out requires.

Important nuance: LVS-clean does NOT guarantee the design is functionally correct. It only guarantees the layout faithfully implements the netlist. If the netlist itself has a bug (wrong logic, timing violation, incorrect constraint), LVS will still pass. That's why functional verification (simulation), STA, and LVS are all independently required - they catch different classes of errors. An LVS-clean, STA-clean chip can still fail functionally if the RTL logic was wrong.

10. What is the seal ring and why does it have special DRC rules?

The seal ring is a continuous ring of metal and active structures running around the perimeter of the die, between the pad ring and the dicing street. Its purposes:

• Mechanically seals the chip edge against moisture ingress (prevents corrosion)

• Guards against plasma-induced damage at the die edge during dicing

• Provides a stress buffer between the die bulk and the scribe line

Special DRC: The seal ring intentionally violates several standard DRC rules - it has very narrow/tight structures and rule violations are expected and foundry-approved. Engineers must either exclude the seal ring cell from DRC or use the foundry-provided waiver file that suppresses known seal ring rule violations. Trying to "fix" seal ring DRC violations is a common mistake by junior engineers.