Verilog
The clearest way to learn Verilog from scratch. You start by learning to think in hardware instead of software, then build up modules, wires, combinational and sequential logic, the all-important blocking vs non-blocking rule, finite state machines, and your first self-checking testbench. Every concept is explained in plain language with examples you can run for free in your browser.
What Verilog Really Is
Describing hardware, not writing software
Your First Module
module, ports, and running it for free online
Wires, Regs, and the Four Values
wire vs reg, 0/1/x/z, and vectors
Operators You Will Actually Use
logic, arithmetic, and the gotcha pair & vs &&
Combinational Logic
assign and always @(*) - output depends only on inputs
if, case, and Avoiding Latches
Clean decision logic that never builds an accidental latch
Sequential Logic and the Clock
Flip-flops, posedge clk, and resets
Blocking vs Non-blocking
The single most important rule in Verilog
Finite State Machines
The pattern behind almost every real controller
Writing a Testbench
Poke your design, watch it, and prove it works
Synthesizable RTL and Next Steps
Write code that becomes real hardware - and where to go next