From Verilog to SystemVerilog

Most RTL today is written in SystemVerilog, which is Verilog plus features that make the code clearer and let the tools catch your mistakes. You do not need all of it for design; a small set of additions makes your RTL noticeably better.

Use logic instead of wire and reg

SystemVerilog adds the logic type, which can be driven in both an assign and an always block. It removes the old wire-versus-reg headache: for almost all RTL you just use logic.

Say what each block is

SystemVerilog gives you always_ff, always_comb, and always_latch. They are not just style: they state your intent, and the tool checks it. If you write always_comb and accidentally create a latch, the tool flags it, catching the exact bug from the if/case lesson automatically.

typedef enum logic [1:0] {RED, GREEN, YELLOW} state_t;
state_t state, next;

always_ff @(posedge clk or posedge rst)
  if (rst) state <= RED;
  else     state <= next;

always_comb begin           // tool errors if this infers a latch
  next = state;
  case (state)
    RED:    next = GREEN;
    GREEN:  next = YELLOW;
    YELLOW: next = RED;
    default: next = RED;
  endcase
end

Enums for state, not magic numbers

A typedef enum gives your FSM states real names instead of raw 2-bit values. The waveform and the code show RED, GREEN, YELLOW, which is far easier to read and debug than 00, 01, 10.

Also handy

• typedef struct to bundle related signals into one named type.
• Packed arrays and multidimensional arrays for clean buses and memories.
• Interfaces to group a whole bus of signals (used heavily in verification).