Low Power Design & UPF
Power is a first-class constraint in modern chips. This path covers the techniques that control it: clock gating, multi-threshold cells, power domains and voltage islands, level shifters and isolation, retention registers, power gating with MTCMOS, and capturing it all as UPF power intent.
Overview
Power consumption is a first-class design constraint in modern chips - especially for mobile SoCs, IoT devices, and high-performance computing. This section cov
Why Low Power Matters
Why Low Power Matters
Clock Gating (ICG)
Clock gating is the single most effective and widely used dynamic power reduction technique. When a register's output won't be used, its clock is disabled - pre
Multi-Threshold Voltage (Multi-Vt)
Every standard cell library provides the same logic functions at multiple threshold voltages. Higher Vt = less leakage but slower. Lower Vt = faster but more le
Power Domains & Voltage Islands
A power domain is a group of logic that shares the same power supply and can be independently powered on/off or operated at different voltages. Modern SoCs have
Level Shifters & Isolation Cells
Level Shifter
Retention Registers
When a power domain is switched off, all register state is lost. Retention registers have a small always-on "shadow latch" that preserves the register value thr
Power Gating (MTCMOS)
Power gating completely cuts the supply to an idle block using a header switch (PMOS) or footer switch (NMOS) cell. Reduces static leakage to near-zero for unus
UPF - Unified Power Format
UPF (IEEE 1801) is the industry-standard format for specifying power intent - power domains, supply nets, power states, isolation, level shifters, retention - i
Low Power Interview Questions (Top 15)
1. Dynamic (switching) power: P = α·C·V²·f - consumed when transistors switch. α = activity factor (fraction of cycles with a transition), C = node capacitance,