Overview

Power consumption is a first-class design constraint in modern chips - especially for mobile SoCs, IoT devices, and high-performance computing. This section covers every low power technique from simple clock gating to full multi-voltage UPF flows.

Dynamic Power

Power consumed when transistors switch: P = α × C × V² × f. α = activity factor, C = capacitance, V = voltage, f = frequency. Dominant in active mode. Reduced by clock gating, operand isolation, voltage scaling.

Static / Leakage Power

Power consumed even when idle - subthreshold leakage current through OFF transistors. Exponentially increases at advanced nodes (<28nm). Reduced by HVT cells, power gating, back-bias. Dominant in standby mode.

Short-Circuit Power

Brief current spike when both PMOS and NMOS are simultaneously ON during a transition. Proportional to input transition time. Minimized by controlling input slew. Usually <10% of total dynamic power.

Ptotal = Pdynamic + Pstatic = α·C·V²·f + Ileak·V Reducing V has the highest impact - dynamic power scales with V², static with V. A 10% voltage reduction = ~19% dynamic power reduction.