Module 32 min

Clock Gating (ICG)

Clock gating is the single most effective and widely used dynamic power reduction technique. When a register's output won't be used, its clock is disabled - pre

Clock gating is the single most effective and widely used dynamic power reduction technique. When a register's output won't be used, its clock is disabled - preventing unnecessary switching of the register and all downstream logic.

ICG Cell - Integrated Clock Gate

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ICG Internal Structure

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Clock Gating in RTL & Synthesis

Verilog - RTL Clock Gating Style

// BAD  -  no clock gating, always switching
always @(posedge clk) begin
  if (en) data_reg <= data_in;
end

// GOOD  -  clock gating inferred by synthesis
// DC/Genus inserts ICG automatically when enable is on clock path
always @(posedge gclk) begin
  data_reg <= data_in;   // no enable needed  -  clock itself is gated
end

// DC command to enable automatic clock gating insertion
set_clock_gating_style   -sequential_cell latch   -minimum_bitwidth 4    # gate registers ≥4 bits wide
compile_ultra -gate_clock

Pro Tip

Clock Gating Efficiency — A typical SoC achieves 20–40% dynamic power reduction from clock gating alone. The key metric is toggle rate - registers that toggle rarely are best candidates. Synthesis tools report clock gating coverage: aim for >80% of registers clock-gated.