Multi-Threshold Voltage (Multi-Vt)

Every standard cell library provides the same logic functions at multiple threshold voltages. Higher Vt = less leakage but slower. Lower Vt = faster but more leakage. Multi-Vt optimization assigns each cell the highest Vt that still meets timing - minimizing total leakage power.

HVT - High Vt

Highest threshold voltage. Lowest leakage - 5–10× less than LVT. Slowest switching speed. Used for non-critical paths with plenty of slack. Default cell for low-power designs.

SVT - Standard Vt

Middle ground. Moderate leakage, moderate speed. Used on semi-critical paths that need some performance boost but not full LVT. Baseline library for most digital designs.

LVT - Low Vt

Lowest threshold voltage. Highest leakage. Fastest switching speed. Used only on critical timing paths where HVT/SVT can't meet timing. Minimize LVT cell count to control leakage.

Multi-Vt in Synthesis

# Step 1: Set HVT as default  -  use LVT only when needed
set_attribute [get_lib_cells */*LVT*] dont_use true
compile_ultra   # compile with HVT+SVT only

# Step 2: Enable LVT on critical paths only
set_attribute [get_lib_cells */*LVT*] dont_use false
compile_ultra -incremental   # LVT used only where timing demands it

# Step 3: Post-compile  -  swap non-critical LVT → HVT
optimize_leakage   # DC command: swaps LVT→HVT where slack allows

# Check Vt distribution
report_power -cell_power   # shows leakage breakdown by cell type

# Target: >70% HVT, <10% LVT for a low-power design