Module 93 min

UPF - Unified Power Format

UPF (IEEE 1801) is the industry-standard format for specifying power intent - power domains, supply nets, power states, isolation, level shifters, retention - i

UPF (IEEE 1801) is the industry-standard format for specifying power intent - power domains, supply nets, power states, isolation, level shifters, retention - in a machine-readable TCL-based format that flows from RTL through synthesis and PD automatically.

Pro Tip

What UPF Does — Without UPF, every tool in the flow (synthesis, PD, STA, simulation) needs to be manually configured for power. UPF is the single source of truth - write it once, all tools read it. Synthesis inserts isolation and level shifter cells automatically. PD tool places them correctly. STA verifies isolation timing.

UPF - Complete Example: 2-Domain Design

## UPF for a design with CPU domain (switchable) + AON domain

## 1. Define supply nets
create_supply_net  VDD      -domain PD_AON
create_supply_net  VDD_CPU  -domain PD_CPU
create_supply_net  GND      -domain PD_AON

## 2. Define power domains
create_power_domain PD_AON   -elements {pmu rtc wake_ctrl}

create_power_domain PD_CPU   -elements {cpu_core l1_cache}   -supply   {primary VDD_CPU}

## 3. Define power states
add_power_state PD_CPU   -state {ON   {-supply_expr {primary == FULL_ON}}}   -state {OFF  {-supply_expr {primary == OFF}}}

## 4. Power switch (header PMOS)
create_power_switch SW_CPU   -domain       PD_CPU   -output_supply_port {vout VDD_CPU}   -input_supply_port  {vin  VDD}   -control_port       {sleep cpu_sleep_n}   -on_state           {on_state {!cpu_sleep_n} {vout == vin}}   -off_state          {off_state {cpu_sleep_n}}

## 5. Isolation cells
set_isolation ISO_CPU_OUT   -domain            PD_CPU   -applies_to        outputs   -clamp_value       0   -isolation_power_net VDD
set_isolation_control ISO_CPU_OUT   -domain            PD_CPU   -isolation_signal  cpu_iso_en

## 6. Retention registers
set_retention RET_CPU   -domain          PD_CPU   -retention_power_net VDD   -save_signal     {cpu_save 1}   -restore_signal  {cpu_restore 1}

## 7. Level shifters (CPU 0.9V → AON 1.0V)
set_level_shifter LS_CPU_AON   -domain      PD_CPU   -applies_to outputs   -threshold  0.5

UPF Flow in the Full Design Flow

Stage	UPF Usage	What Happens
RTL Simulation	read_upf in simulator	Power-aware simulation - verifies save/restore sequences work
Synthesis (DC/Genus)	read_upf before compile	Auto-inserts isolation, level shifter, retention cells
Physical Design (Innovus/ICC2)	read_upf at start	Places special cells correctly, routes power switch, creates power domains in floorplan
STA (PrimeTime)	read_upf for power state analysis	Checks isolation cell timing, level shifter paths, retention setup/hold
Formal Verification	JasperGold Power Apps	Formally verifies UPF intent matches RTL behavior