Low Power Interview Questions (Top 15)

1. What are the three types of power dissipation in a CMOS circuit?

1. Dynamic (switching) power: P = α·C·V²·f - consumed when transistors switch. α = activity factor (fraction of cycles with a transition), C = node capacitance, V = supply voltage, f = clock frequency. Dominant in active mode.

2. Static (leakage) power: P = I_leak × V - consumed even when idle due to subthreshold conduction, gate tunneling, and drain-induced barrier lowering. Becomes dominant at advanced nodes (<28nm) due to thin oxides and low threshold voltages.

3. Short-circuit power: Brief current spike when both PMOS and NMOS conduct simultaneously during input transitions. Proportional to input slew rate. Typically <10% of total power.

2. What is clock gating and why does it save power?

Clock gating disables the clock to a register (or group of registers) when its output won't be used. This prevents the register from switching - saving the dynamic power of the FF toggle AND all downstream combinational logic transitions driven by that FF output.

An ICG (Integrated Clock Gate) cell uses a latch + AND gate. The latch samples the enable signal on the clock low phase - ensuring the enable is glitch-free before it gates the clock. The AND gate produces the gated clock GCLK = CLK AND EN_latched.

Savings: 20–40% dynamic power reduction typically. The latch in the ICG ensures no glitch reaches the register clock pins - a pure AND gate without the latch could create runt pulses.

3. What is the difference between HVT, SVT, and LVT cells?

These are the same logic function implemented at different threshold voltages:

HVT (High Vt): Highest threshold → lowest leakage (5–10× less than LVT) → slowest speed. Used on non-critical paths. Default cell for power optimization.

SVT (Standard Vt): Middle ground. Moderate leakage and speed. Used on semi-critical paths.

LVT (Low Vt): Lowest threshold → highest leakage → fastest speed. Used only on critical timing paths where HVT/SVT can't meet timing. Should be minimized.

Synthesis strategy: Start with all HVT. Compile for timing. Synthesis automatically promotes cells to SVT/LVT only where needed. After compile, use optimize_leakage to swap non-critical LVT back to HVT. Target: >70% HVT cells.

4. What is a power domain? Why are multiple power domains needed?

A power domain is a group of logic cells that share the same power supply and can be controlled together - powered on/off or operated at a different voltage.

Multiple domains are needed because different blocks have different power requirements:

• CPU: needs high performance → high voltage during active use, but can power off during sleep

• Modem: only needed during calls - can be completely off otherwise

• Always-on (PMU, RTC): must never power off to maintain system state and wake capability

• I/O: operates at 1.8V/3.3V regardless of CPU voltage

Without multiple domains, saving power in one block requires reducing voltage for ALL blocks - not possible when some blocks need high voltage for performance.

5. What is isolation cell? Where must it be placed and why?

When a power domain powers OFF, its flip-flop outputs become undefined (floating - neither 0 nor 1). These floating signals can corrupt the always-on logic receiving them (cause false transitions, metastability, or excessive current draw).

Isolation cells clamp the output of a powered-off domain to a defined logic value (0 or 1) as specified in UPF.

Critical placement rule: Isolation cells MUST be placed in the always-on (receiving) domain - powered from VDD_AON. If placed in the switchable domain, they would power off together with the domain and fail to isolate. This is a common design error that causes silicon failures.

6. What is power gating? What are header and footer switches?

Power gating completely disconnects a block's power supply using a transistor switch, reducing its leakage to near-zero during idle periods.

Header switch (PMOS): Placed between VDD and the block's virtual VDD (VDD_SW). PMOS conducts when gate is LOW (SLEEP_N). Cuts the VDD supply. Area-inefficient (PMOS needs larger W for same drive strength).

Footer switch (NMOS): Placed between GND and the block's virtual GND (GND_SW). NMOS conducts when gate is HIGH (SLEEP). Preferred - NMOS has higher mobility, smaller area for same drive strength.

Rush current: When powering ON, capacitances charge rapidly → large inrush current spike. Power switches are typically woken up in segments (staggered enable) to limit rush current and IR drop on the main supply rail.

7. What is a retention register and when is it used?

A retention register is a special flip-flop with a small always-on shadow latch that preserves the register's value through a power-off cycle.

Structure: Main FF (powered from domain supply) + Shadow latch (powered from AON supply, ~5–10% area of main FF).

Operation:

• SAVE: Shadow latch captures main FF value just before power-off

• Power off: Main FF loses power (state gone), shadow latch retains value on AON supply

• RESTORE: After power-on, main FF reloads from shadow latch

Used for: configuration registers, CPU PC/registers, cache tags - any state that's expensive to reconstruct.

NOT used for: data registers that can be reloaded from memory.

8. What is UPF and what does it specify?

UPF (Unified Power Format, IEEE 1801) is a TCL-based standard for describing power intent in a design. It's the single source of truth for the entire design flow.

UPF specifies:

• Power domains: Which logic cells belong to which domain

• Supply nets: VDD, GND, virtual rails

• Power switches: Header/footer switch placement and control

• Power states: Valid combinations of supply conditions (ON, OFF, retention)

• Isolation cells: Where, which signal controls, clamp value

• Level shifters: At domain boundaries with different voltages

• Retention registers: Which domains need retention, save/restore signals

Tools that read UPF: DC/Genus (synthesis), Innovus/ICC2 (PD), PrimeTime (STA), simulators (power-aware sim), JasperGold (formal).

9. What is the correct power-up and power-down sequence for a power-gated domain?

Power-down sequence:

• Software initiates sleep request

• Hardware flushes/saves context to memory or retention registers (SAVE pulse)

• Assert isolation enable signal → outputs clamped to safe value

• Assert sleep signal → power switch cuts supply

• Domain is now OFF - isolation cells holding outputs, retention latches holding state

Power-up sequence:

• Deassert sleep signal → power switch connects supply (staggered for rush current)

• Wait for supply to stabilize (power-on reset)

• RESTORE pulse → retention registers reload main FFs

• Deassert isolation → outputs drive normally

• Resume operation

Incorrect sequence (e.g., removing isolation before power is stable) causes glitches that corrupt always-on domain state.

10. What is level shifter and when is it needed?

A level shifter is required whenever a signal crosses between two domains operating at different supply voltages.

Why: A logic "1" from a 0.6V CPU domain is only 0.6V. A 1.8V I/O cell may not recognize 0.6V as a valid logic "1" (its Vil/Vih thresholds are higher). The signal must be amplified to the destination domain voltage.

Types:

• Low-to-high LS: CPU (0.6V) → I/O (1.8V)

• High-to-low LS: I/O (1.8V) → CPU (0.6V)

• Enable LS: combines level shift + isolation enable

Placement: Level shifters are inserted by synthesis when UPF specifies the domain boundaries. In PD, they're placed near the domain boundary to minimize wire length for the shifted signal.

Not needed when both domains operate at the same voltage - even if they're separate power domains (e.g., two 1.0V domains share the same voltage but can be independently switched off).

11. How does operand isolation save power?

Operand isolation prevents unnecessary switching of combinational logic inputs when the output won't be used - saving the dynamic power of the combinational cloud.

Example: A 32-bit multiplier takes data_a and data_b as inputs. If the output is not valid (mult_enable = 0), the inputs still toggle as upstream logic switches → the entire multiplier switching tree dissipates power uselessly.

Fix: Add AND gates at the multiplier inputs: data_a_gated = data_a AND mult_enable. When enable = 0, inputs are clamped to 0 → no switching through the multiplier.

Synthesis inserts this automatically when directed: compile_ultra -power with set_operand_isolation_style. Different from clock gating - operand isolation gates data paths, not clock paths.

12. What is dynamic voltage and frequency scaling (DVFS)?

DVFS reduces both voltage and frequency together when full performance isn't needed. Since dynamic power scales as V²×f, reducing both gives cubic power reduction.

Example: At full performance (1.0V, 1GHz) P = P_ref. At half performance (0.7V, 500MHz): P = (0.7/1.0)² × (0.5/1.0) × P_ref = 0.49 × 0.5 × P_ref = 0.245 P_ref → 75% power reduction at 50% performance!

Implementation: PMIC (Power Management IC) adjusts supply voltage. PMU (Power Management Unit) in the SoC adjusts PLL frequency. The two must be coordinated - voltage must be raised BEFORE frequency increases (setup time margin), and frequency must be lowered BEFORE voltage decreases.

UPF specifies the voltage levels for each operating point (OPP - Operating Performance Point).

13. What power analysis tools are used at sign-off?

• Synopsys PrimePower / PrimeTime PX: Industry-standard power sign-off. Uses SAIF (Switching Activity Interchange Format) or VCD from simulation to get accurate activity factors. Reports dynamic + leakage power per cell and hierarchically.

• Cadence Voltus: Cadence's power integrity and analysis tool. Integrates with Innovus. Performs IR drop + power analysis simultaneously.

• Mentor PowerPro / Questa Power: RTL-level power analysis and optimization recommendations.

• SAIF file: Compact switching activity file from simulation - used as input to power tools for accurate α values per net.

Sign-off power analysis is done at multiple scenarios: active mode (worst-case dynamic), idle mode (leakage dominant), and sleep mode (power gating verification).

14. What is always-on logic and why must it be treated specially?

Always-on (AON) logic is logic that remains powered even when other domains are off - typically the PMU, RTC, wake-up controller, and power sequencing FSM.

Special treatment required:

• Connected to VDD_AON: All cells in AON domain must use the always-on supply - if any cell uses the switchable supply, it powers off when the domain sleeps

• HVT cells preferred: AON logic runs 24/7 - leakage here directly impacts standby battery life. Use HVT aggressively

• Minimal logic: Keep AON domain as small as possible - every gate here leaks continuously

• Isolation cells here: Must be in AON domain to protect from floating inputs when other domains are off

• Retention register shadow latches: Powered from AON supply

A common bug: a gate in the "always-on" domain accidentally connected to a switchable supply - it powers off when it shouldn't, causing system hang.

15. How do you verify that your UPF implementation is correct?

UPF verification requires multiple steps across the flow:

1. Power-aware simulation: Run RTL simulation with UPF loaded. Simulator models domain power states - signals in OFF domains become X. Verify save/restore sequences produce correct Q outputs. Verify no X propagation into always-on domain from missing isolation.

2. Synthesis check: After compile with UPF, check that all required isolation, level shifter, and retention cells were inserted: check_mv_design in DC.

3. Formal verification: Cadence JasperGold Power Apps or Synopsys VC Formal formally verify that the UPF intent (isolation, retention) is correctly implemented in the gate-level netlist.

4. STA power-state analysis: PrimeTime reads UPF and checks timing for each power state - isolation cell timing, level shifter paths, and that disabled paths are correctly excluded.

5. Post-layout check: Verify power switch placement, isolation cell in correct domain, retention register shadow on AON rail - using LVS-like connectivity checks.