Clock Domain Crossing
Almost every chip has multiple clocks, and signals crossing between them cause some of the hardest bugs in digital design. This path teaches clock domain crossing from the ground up: why metastability happens and cannot be timed away, the two-flop synchronizer, why buses need gray code, asynchronous FIFOs, handshake and pulse synchronizers, reset synchronization, and how CDC is actually verified.
8 modulesIntermediateVerilogSystemVerilogCDC analysis
1
Why Clock Domain Crossing Matters
What breaks when a signal crosses clocks
7 minFree
2
Metastability, Explained
Why it happens and why you can only manage it
8 minFree
3
The Two-Flop Synchronizer
The standard fix for a single-bit crossing
8 minFree
4
Buses and Gray Code
Why you cannot just synchronize a bus bit by bit
9 minFree
5
The Asynchronous FIFO
The standard way to move data between clocks
11 minFree
6
Handshake and Pulse Synchronizers
Crossing pulses and arbitrary data safely
9 minFree
7
Reset Synchronization
Asserting async, removing it synchronously
8 minFree
8
CDC Verification and Common Mistakes
How CDC is checked, and the traps to avoid
8 minFree