The Two-Flop Synchronizer

The two-flop synchronizer is the workhorse of CDC. It is the correct, standard way to bring a single-bit signal safely into a new clock domain.

How it works

Place two flip-flops in series, both clocked by the destination clock. The first flop samples the asynchronous input and may go metastable. By the time the next destination edge arrives, that first flop has almost certainly settled, so the second flop captures a clean, stable value to hand to the rest of the logic.

// Two-flop synchronizer for a single-bit signal
module sync2 (
  input  wire clk_dst,    // destination clock
  input  wire async_in,   // signal from another domain
  output reg  sync_out
);
  reg meta;
  always @(posedge clk_dst) begin
    meta     <= async_in; // may go metastable
    sync_out <= meta;     // settled, safe to use
  end
endmodule

The rules that make it valid

1. Both flops use the destination clock, and only the destination clock.
2. Put no combinational logic between the two flops - the first flop needs the full cycle to settle.
3. Use it only for a single bit, or for signals where each bit is independent.

What it costs and what it needs

• Latency: the signal appears one to two destination cycles later.
• The input must stay stable long enough to be caught, so it suits slow-changing levels and control signals.