Physical Design
The full backend flow as a working PD engineer runs it. You start from a synthesized netlist and take it to a clean GDSII, learning floorplanning, power planning, placement, clock tree synthesis, routing, and timing closure along the way.
Introduction to Physical Design
Physical Design converts a synthesized gate-level netlist into a manufacturing-ready GDS layout, determining the physical placement, power, clock, and routing o
Floorplanning
Anatomy of a Chip Die - Every Term Explained
Power Planning
Building the power distribution network: pads, core ring, stripe mesh, M1 rails and via arrays; IR drop, electromigration, decaps and power domains.
Placement
Global, legalization and detailed placement: rows and sites, timing- and congestion-driven placement, density, blockages and place-opt.
Clock Tree Synthesis (CTS)
How CTS builds a real, balanced clock network: topologies (H-tree, spine, mesh), skew, latency, useful skew and the hold it exposes.
Routing
Global and detailed routing: the metal stack, tracks, vias, congestion, NDR and shielding, crosstalk and antenna, DRC/LVS and ECO routing.
Physical Verification
Signoff PV: DRC (spacing/width/enclosure), LVS device-by-device compare, the antenna effect and its fixes, ERC and DFM, and the tape-out gate.
PD Tool Knowledge
The place-and-route tools: what a PnR tool runs, Cadence Innovus and Synopsys ICC2/Fusion command flows, OpenROAD/OpenLane, and how to compare them.
Congestion Analysis and Fixes
Why routing fails, and how to find the cause
IR Drop and Power Integrity
When the power grid cannot keep up
The ECO Flow
Making small, surgical late-stage changes