Routing
Global and detailed routing: the metal stack, tracks, vias, congestion, NDR and shielding, crosstalk and antenna, DRC/LVS and ECO routing.
After placement every cell has a location, but the pins are still islands: nothing is physically connected. Routing draws the actual metal wires and vias that join every pin the netlist says should be joined, tens of millions of connections on a real SoC. Those wires must connect exactly what the netlist demands, obey every foundry design rule, stay short enough for timing and power, and not couple noise into each other. It is done in two phases, global then detailed, and only after it is done is your timing finally built on real wire delays.
The two-phase routing flow
Routing is split so the hard problem stays tractable. Global routing plans: it divides the core into a coarse grid of global cells (gcells), decides which gcells and which layers each net will pass through, and builds a congestion map without drawing a single real wire. Detailed routing commits: working within the plan, it assigns each net to actual tracks, drops the vias for every layer change, and fixes design-rule violations down to the exact geometry.
The metal stack
Signals travel on a stack of metal layers, from M1 up to M8-M15 at advanced nodes. Lower layers (M1-M2) are thin and tight-pitched for short local connections and reaching cell pins; upper layers are wide and thick, with low resistance, for long global signals, the clock, and the power grid. Each layer has a preferred routing direction and they alternate, horizontal on one, vertical on the next, so wires on adjacent layers cross rather than run alongside each other, which keeps coupling down and makes the grid routable.
Vias, the vertical connections
A via is a metal plug that connects two adjacent layers. A via between M1 and M2 is a V1, between M2 and M3 a V2, and so on. Vias have real resistance and limited current capacity, so high-current or wide nets use via arrays (many vias in parallel) to cut resistance and survive electromigration. A missing or broken via is an open circuit and shows up as an LVS failure.
Tracks, grid and pitch
Each layer is divided into routing tracks, parallel lines spaced at the layer's minimum wire pitch. One track holds one wire, so the number of tracks crossing a region is the routing supply there. When more nets need to cross a region than there are tracks, the region overflows: that is congestion, and it is why global routing builds a congestion map before any wire is drawn.
Global routing and the congestion map
Global routing assigns every net a rough path through the gcell grid and adds up, per gcell edge, how many wires want to cross versus how many tracks exist. Any gcell where demand exceeds supply is an overflow, a hotspot the detailed router will not be able to solve. Overflows this early are a placement problem, not a routing one: the fix is to go back and spread the cells (padding, blockages, re-placement), not to push harder in the router.
Track assignment and detailed routing
Between the two phases, track assignment pins the long straight segments of each net onto specific tracks. Detailed routing then finishes the job locally: it connects pins to those segments, inserts vias, and iterates a search-and-repair loop that rips up and reroutes wires until every design rule is clean. This is where the millions of tiny geometry decisions actually happen.
Non-default rules, shielding and the clock
Not every net is routed the same way. Non-default rules (NDR) give chosen nets extra width and spacing, wider metal lowers resistance and electromigration risk, extra spacing cuts crosstalk. The clock is the classic NDR customer, often routed double-width, double-spaced and sometimes shielded: grounded wires run beside it so neighbouring switching cannot jitter the clock edge.
Signal integrity: crosstalk and antenna
Two physical effects surface at routing. Crosstalk is coupling between wires that run parallel for a long distance: an aggressor net's switching injects noise and delay onto a victim net, fixed with spacing, shielding or NDR. The antenna effect is a manufacturing hazard, a long stretch of metal built up before it connects to a gate can collect enough charge during fabrication to damage the transistor; it is fixed by antenna diodes or by jumping the net up to a higher layer to break the long segment.
DRC and LVS after routing
Once wires exist they must pass physical verification. DRC checks the geometry against the foundry rules; LVS checks that the drawn layout matches the netlist exactly. Routing also has to satisfy metal-density (fill) rules so chemical-mechanical polishing stays uniform. A clean route is one that is not just connected but DRC-correct and LVS-clean.
| DRC rule | What it constrains | Why a violation hurts |
|---|---|---|
| Spacing | Minimum gap between same-layer wires | Shorts / yield loss at manufacture |
| Width | Minimum wire width per layer | Higher resistance, IR drop, EM failure |
| Via rule | Legal via size, enclosure and spacing | Open or unreliable layer connection |
| Min area | Smallest allowed metal shape | Unmanufacturable slivers of metal |
| Density / fill | Metal coverage per region | Uneven CMP polishing, dishing |
| Antenna | Max metal area on a net before a gate | Charge damage to transistor gates |
ECO routing
Late fixes, a timing ECO, a functional patch, a hold-buffer insertion, should not disturb the millions of nets that are already clean. ECO routing routes only the changed nets incrementally, reusing spare cells where possible, so a small change stays a small change instead of forcing a full re-route.
Key routing commands
| Command | Tool | Purpose |
|---|---|---|
| route_auto / route_opt | ICC2 / Fusion Compiler | Global + track + detailed routing with optimisation |
| route_global / route_track / route_detail | ICC2 | Run each routing phase individually |
| routeDesign / globalRoute / detailRoute | Innovus | Full or per-phase routing |
| create_routing_rule / set_clock_routing_rule | Both | Define and apply non-default rules (NDR) |
| report_congestion | Both | Global-route overflow / congestion map |
| verify_drc / check_lvs | Both | Design-rule and layout-vs-schematic checks |
Recap: routing turns placed pins into real metal in two phases: global plans paths through gcells and exposes congestion, detailed commits every wire to a track with vias and cleans DRC. Layers alternate direction and get thicker toward the top; the clock and critical nets get NDR and shielding; and the route is only finished when it is DRC-correct, LVS-clean and free of crosstalk and antenna problems.