Routing
Metal Layers - Why Multiple Layers Exist
Start Here - What Is Routing? — After placement, you know where every cell sits, but the cells are still disconnected - like buildings in a city with no roads between them. Routing draws the actual metal wires that connect every cell pin to every other cell pin according to the netlist. A modern chip might have 50–200 million net connections to route. The wires must: (1) actually connect what the netlist says, (2) satisfy all foundry DRC rules, (3) minimize wire length (affects timing and power), and (4) not cause crosstalk noise. This is done in two phases: global routing (plan the routes) and detailed routing (draw the actual shapes).
Metal Layers - Why Multiple Layers Exist
Why Do Chips Have Multiple Metal Layers? — If you had only one metal layer, wires couldn't cross without shorting - like a city with only one road that can never have intersections. Multiple metal layers (M1, M2, M3… up to M15+ at advanced nodes) solve this: each layer's wires run in one direction (alternating horizontal/vertical), and vias connect between layers wherever a wire needs to change layers or connect to another wire. Lower metals (M1, M2) have thin, tight-pitch wires for local connections. Upper metals (M8+) have wide, coarse wires for global signals, power, and clock distribution - they carry more current and span longer distances.
What Is a Via? How Do Layers Connect?
Via - The Vertical Connection
A via is a small metal pillar that connects two adjacent metal layers vertically. Via between M1 and M2 is called V1 (Via 1). Between M2 and M3 is V2, etc. Vias have limited current capacity - high-current nets need via arrays (many parallel vias) to prevent electromigration. A missing or broken via = open circuit = LVS failure.
Preferred Routing Direction
Each metal layer has a preferred routing direction: M1 vertical, M2 horizontal, M3 vertical, M4 horizontal... (alternating). This orthogonal arrangement minimizes parallel-running wires on adjacent layers (reduces coupling capacitance / crosstalk). Routing against preferred direction is allowed but penalized by the router.
Routing Track
The routing grid on each metal layer is divided into tracks - parallel lines at the minimum wire pitch. Each track can hold one wire. The number of tracks in a routing channel = available routing resources. When more wires need to cross a region than there are tracks → routing overflow / congestion → DRC violations or unroutable design.
Metal Layer Stack (Color-Coded)
| DRC Rule | Definition | Violation Impact |
|---|---|---|
| Spacing | Minimum distance between same-metal parallel wires | Short circuit risk, manufacturing defects |
| Width | Minimum wire width per metal layer | Higher resistance → IR drop, EM failure |
| Via enclosure | Metal must extend beyond via by minimum amount | Broken via connection on manufacturing variation |
| Antenna | Limits ratio of metal area to gate oxide area | Gate oxide damage during plasma etch |
| Density | Min/max metal fill requirements per layer | CMP non-uniformity → dishing/erosion |