Power Planning
The positive voltage rail. At 28nm ≈ 0.9–1.05V, at 5nm ≈ 0.65–0.8V. Every cell's PMOS transistors connect here. When VDD wire has resistance, current causes a v
Start Here - Why Does Every Cell Need VDD and VSS? — Every single logic gate needs two power connections: VDD (positive supply, e.g. 1.0V) and VSS (ground, 0V). Without these, no transistor can switch. A chip with 10 million cells all simultaneously drawing current needs a power delivery highway network. Power planning builds this network. Get it wrong → cells starve for power → they slow down → timing failures.
VDD - Power Supply Rail
The positive voltage rail. At 28nm ≈ 0.9–1.05V, at 5nm ≈ 0.65–0.8V. Every cell's PMOS transistors connect here. When VDD wire has resistance, current causes a voltage drop - cells at the far end see less than VDD → slower switching → potential timing violations.
VSS - Ground Rail
The 0V reference. Every cell's NMOS transistors return current to VSS. Must also be low-resistance - a "bouncing" VSS from high return currents can cause ground bounce noise that flips logic states erroneously (functional failure!).
The Power Delivery Hierarchy
Current path: PCB → Package pins → Solder bumps/Bond wires → I/O pads on die edge → Power rings (thick metal rings around core) → Power stripes (wide wires criss-crossing the core on upper metals) → Power rails inside std cell rows → Individual cell VDD/VSS pins. Each step adds resistance.
Decap Cells
Decoupling capacitor cells placed between VDD and VSS in empty spaces. They act as local charge reservoirs - when many cells switch simultaneously and demand a sudden surge of current, the decaps supply it instantly without waiting for current to travel from far-away pads. Reduces dynamic IR drop peaks.
V_drop = I (current drawn by cells) × R_metal (wire resistance) → Cell sees VDD − V_dropR = ρ × L / (W × T) where L=length, W=width, T=thickness, ρ=metal resistivity. Double W → half R → half IR dropJ = I / A must be < J_max from Black's equation: J_max = A × e^(-Ea/kT). Exceed this → wire fails in product lifetimeConsequence of IR Drop - A Real Example — If VDD drops 10% (1.0V → 0.9V) in a hot corner of the chip, transistors in that region become ~20% slower. Paths that barely meet 5ns timing now take 6ns → new setup violations appear at sign-off that weren't visible in pre-IR-drop STA. This is why IR drop is a mandatory sign-off check - STA without IR drop is not sign-off quality.
Power Grid Topology
IR Drop
Voltage reduction along the power rail due to resistive metal. Static IR drop: DC current × metal resistance. Dynamic IR drop: transient switching currents cause instantaneous dip. Must keep < 5–10% of VDD.
Electromigration (EM)
Gradual movement of metal atoms due to electron flow (current density). Causes open circuits over time. Limit: J < Jmax for each metal segment. Wider wires or via arrays reduce EM risk.