Power Planning
Building the power distribution network: pads, core ring, stripe mesh, M1 rails and via arrays; IR drop, electromigration, decaps and power domains.
Before a single signal is routed, every one of your hundreds of thousands of cells needs a solid, steady supply of VDD and VSS. Power planning (also called the power distribution network, or PDN) builds that supply grid: a hierarchy of metal that carries current from the package pads all the way down to each cell, without the voltage sagging too far along the way. It is done right after floorplanning, because the grid has to be in place before placement and routing fill the core.
What the PDN has to guarantee
The PDN has one job: deliver a stable voltage to every cell under worst-case current draw. Three physical effects threaten that. IR drop, resistance times current, means the voltage at a far cell is lower than at the pad; too much drop and cells slow down or fail. Electromigration (EM), sustained high current density slowly erodes metal until it opens. And di/dt noise, sudden switching current the grid cannot supply fast enough, which is smoothed by decoupling capacitors. A good power plan keeps IR drop within budget (often a few percent of VDD), stays under EM current limits, and has enough decap to ride out transients.
The power hierarchy: pads to cells
Power flows down a fixed hierarchy: package pads bring VDD and VSS onto the die; a core ring, a wide metal loop on upper layers, carries it around the core boundary; power stripes (straps) cross the core in a mesh, tapping the ring; standard-cell rails (M1, one VDD and one VSS per row) run along every row; and finally each cell connects its power pins to those rails. Vias stitch every level to the one below.
The core ring and power stripes
The core ring is a wide, low-resistance loop of VDD and VSS around the core, sized to carry the whole block's current. From the ring, stripes run across the core on upper metal layers, verticals on one layer, horizontals on the next, forming a grid. A denser grid (more stripes, wider metal) lowers resistance and IR drop but steals routing tracks from signals, so the stripe width and pitch are a direct trade-off between a stiff supply and routability.
Standard-cell rails
At the bottom of the hierarchy, every standard-cell row has an M1 VDD rail along one edge and an M1 VSS rail along the other. Because adjacent rows are flipped and abut, they share rails, one rail feeds the row above and the row below. The mesh stripes drop down through vias onto these rails, and each cell's power pins sit right on them, so the cell is powered the moment it is placed in a legal row.
Vias and via arrays
Every layer change in the PDN is a via, and power vias carry a lot of current, far more than a signal via. A single via would melt (EM failure) or add too much resistance, so power connections use via arrays: many vias in parallel at each ring-to-stripe and stripe-to-rail junction. More vias means lower resistance and higher current capacity, which is why via count is a real knob in power planning.
Decoupling capacitors
When a large block switches, it demands a burst of current the grid cannot deliver instantly through its resistance and inductance, the local voltage dips (di/dt droop). Decoupling capacitors (decaps) placed near switching logic act as tiny local reservoirs, supplying that burst and refilling between edges. Filler decap cells are spread through the core, with extra near high-activity blocks, to keep the supply quiet.
Building and checking the plan
From the target power and voltage, work out peak and average current per region so the grid can be sized for it.
Choose metal layers, widths and pitch for the ring and the vertical/horizontal stripe mesh.
Create the per-row M1 rails and drop via arrays from stripes to rails.
Insert decoupling capacitors, weighted toward high-activity regions.
Run static and dynamic IR-drop and electromigration analysis; widen metal or add vias/stripes where the budget is exceeded.
Multiple power domains
Modern SoCs are not a single supply. Low-power designs split the chip into power domains that can run at different voltages or be switched off entirely, described in a UPF file. That adds power switches (header/footer cells) for the switchable domains, always-on grids for logic that must never lose power, level shifters between domains, and isolation cells, all of which the power plan has to route and verify. (The Low Power path covers the methodology in depth.)
Power-planning checks
| Check | What it measures | Healthy target |
|---|---|---|
| Static IR drop | Average voltage drop from pad to cell | Within budget, often < ~2-5% of VDD |
| Dynamic IR drop | Instantaneous droop under switching | Below the timing-signoff margin |
| Electromigration | Current density in metal and vias | Under the foundry current limits |
| PDN resistance | Effective resistance pad-to-rail | Low and uniform across the core |
| Decap coverage | Local capacitance vs switching demand | Enough near high-activity blocks |
Power planning is a floorplan-stage decision you cannot easily undo later. If the grid is too weak you will only discover it as IR-drop and EM failures after routing, when fixing it means ripping up signal routes to make room for more stripes. Budget the grid generously up front, then recover routing resources only where analysis proves you can.
Recap: the PDN carries power from pads through the core ring, into a stripe mesh, down via arrays onto per-row M1 rails, and finally into each cell. Size it for IR drop and EM, add decaps for di/dt, handle power domains for low-power designs, and sign it off with IR-drop and EM analysis before you trust the rest of the flow.