Placement

Start Here - What Exactly Gets Placed? — After synthesis, you have a gate-level netlist - a list of cells (AND2, DFF, BUF...) and wires connecting them. But they have no physical location yet - it's like having all the components of a city but no map showing where each building goes. Placement decides the X,Y coordinates of every standard cell inside the core area. This decision is critical: cells that are logically connected should be physically close → shorter wires → less resistance and capacitance → faster timing → less power. Bad placement = long wires everywhere = timing closure becomes nearly impossible.

Standard Cell Rows - The Shelf System — The core area is divided into horizontal strips called rows, all of the same height (determined by the technology node, e.g. 0.27µm tall at 28nm). Every standard cell has exactly this height, so all cells snap perfectly into rows - like books on a shelf. Each row has VDD and VSS power rails running horizontally through it. Cells in adjacent rows are flipped upside down so they share the power rails between rows - this halves the number of power stripes needed. Cells must be placed aligned to the row grid AND to a horizontal placement site (typically 0.09µm pitch). Any deviation = legalization violation.