Floorplanning
Anatomy of a Chip Die - Every Term Explained
Start Here - What Is a Chip Physically Made Of? — Before floorplanning makes sense, you need to understand what actually sits on a piece of silicon. A chip is a layered sandwich: a silicon substrate at the bottom, transistors built on top of it, then alternating layers of metal wires and insulating oxide on top. All of these layers together form the die. Floorplanning is the step where you decide where on that silicon each piece of logic goes.
Anatomy of a Chip Die - Every Term Explained
Every Floorplan Term - Explained From Scratch
① Die
The die (also called a chip) is a single rectangular piece of silicon cut from a wafer. Hundreds of identical dies are fabricated simultaneously on one 300mm wafer, then sawn apart. The die includes everything - pads, power rings, seal ring, and the core logic. Die area is measured in mm². Larger die = more expensive (cost scales roughly with area²).
② I/O Pads
I/O pads are the connection points between your chip and the outside world (PCB board, other chips). They live around the perimeter of the die. Each pad has:
• A signal pad - for data inputs/outputs (bidirectional, input-only, or output-only) • A power pad - for VDD (positive supply) and VSS (ground). Multiple VDD/VSS pads are used because each pad can only carry limited current.
In your SDC file, get_ports refers to these pad signals. The set_input_delay and set_output_delay constraints model the timing from/to these pads.
③ Core Area vs Die Area
The core area is the inner rectangle where all your synthesized logic (standard cells + macros) lives. The die area is the full silicon including the pad ring around it.
Think of it like a room (core) inside a building (die). The walls of the building hold the doors (I/O pads). The room is where all the furniture (logic) goes. The gap between the room walls and the building walls is used for corridors (power rings, routing channels) - this gap is called the core-to-IO margin (typically 20–50 µm).
④ Standard Cell
A standard cell is a pre-designed, pre-characterized logic gate (AND, OR, NAND, flip-flop, buffer, mux, etc.) from the technology library. Every standard cell has:
• A fixed height (e.g., 12-track height in 7nm) - all cells in the same technology have the same height • A variable width depending on complexity (a 4-input NAND is wider than a 2-input AND) • VDD and VSS rails running along the top and bottom edges
Because all standard cells have the same height, they can be placed in rows like books on a shelf. The synthesis tool converts your Verilog RTL into thousands of standard cell instances. The PD tool then physically places them in the rows.
⑤ Hard Macro
A hard macro is a large, pre-designed block with a fixed physical layout - you cannot synthesize it or change its internals. Common examples:
• SRAM - On-chip memory. Your CPU's cache or register file. Designed by memory compilers with optimized bit-cell layout. • PLL (Phase-Locked Loop) - Clock generator circuit. Analog design, cannot be synthesized. • ROM - Read-only memory for boot code or lookup tables. • Analog IP - ADC, DAC, SerDes PHY - all analog, all hard macros.
Hard macros are placed first during floorplanning, before any standard cells. Their position determines how efficiently the remaining logic can be placed and routed.
⑥ Macro Halo (Keepout Zone)
A macro halo is an exclusion zone around each hard macro where standard cells cannot be placed. Typical size: 2–5 µm on all sides.
Why? Because the macro's internal structure needs routing access around its edges (for signal and power connections). If standard cells are placed right up against the macro wall, the router has no room to route those connections - creating a routing deadlock.
It's like leaving a sidewalk around a building so people can walk to the entrance - if you park cars right up to the walls, nobody can get in.
⑦ Utilization
Utilization = how full is your core area with actual logic?
Utilization = (Total std cell area) / (Core area) × 100%
Why not 100%? Because you need space for: • Routing channels (wires between cells) • Clock buffers and power supply cells inserted during PD • Filler cells and decap cells • Spare cells for post-silicon ECO
Rule of thumb: 60–75% utilization is the sweet spot. Below 60% = die is wastefully large (costs more money per chip). Above 80% = routing becomes extremely congested and timing closure becomes very difficult or impossible.
⑧ Aspect Ratio
Aspect ratio = Core height / Core width. An aspect ratio of 1.0 means a perfect square core.
Most designs target 1:1 (square) because it minimizes average wire length (which minimizes delay and power). Non-square shapes are used when: • I/O pad constraints require a specific shape (e.g., a chip with many memory interfaces on one side) • Large hard macros naturally push the aspect ratio • The package dictates the die shape
Extreme aspect ratios (e.g., 3:1 - very tall and thin) cause problems: clock distribution becomes unbalanced, wire lengths increase, and some areas become routability bottlenecks.
Utilization - Visualized
Formulas with Worked Example
Utilization = (Total Standard Cell Area) / (Core Area) × 100%Core Area = Total Cell Area / Target UtilizationAR = Core Height / Core Width (1.0 = square)Worked Example - How to Size a Floorplan — Given: Synthesis reports total cell area = 4.8 mm². Target utilization = 70%. Preferred square core. Step 1: Core Area = 4.8 / 0.70 = 6.86 mm² Step 2: For AR = 1.0 (square): Width = Height = √6.86 = 2.62 mm × 2.62 mm Step 3: Add core-to-IO margin (say 40 µm each side): Die = (2.62 + 0.08) × (2.62 + 0.08) = 2.70 mm × 2.70 mm Step 4: Verify: Do the hard macros (SRAMs) fit? If SRAM is 1.2 mm × 0.8 mm + halo, it needs ~1.25 mm × 0.85 mm footprint - this fits in the 2.62mm core.
Floorplan Parameters - With Full Explanation
| Parameter | Typical Value | What It Means | If You Get It Wrong |
|---|---|---|---|
| Core Utilization | 60–75% | Percentage of core area filled with standard cell logic. The rest is routing space + buffers. | >80%: router can't fit all wires → routing overflow → unrouteable design. <50%: die is larger than needed → higher cost per chip. |
| Aspect Ratio | 1:1 (square) | Core height divided by core width. 1.0 = perfect square. Controls the shape of the chip. | Extreme ratios (3:1) make clock distribution and power delivery much harder. I/O pad count may also force non-square shapes. |
| Core-to-IO margin | 20–50 µm | The gap between the outer edge of the core and the inner edge of the I/O pad ring. Used for power rings (VDD/VSS) and routing channels to connect pads to core logic. | Too narrow: power rings don't fit, I/O connections cannot be routed. Too wide: wastes die area. |
| Macro halo | 2–5 µm | The empty forbidden zone around each hard macro where NO standard cells are placed. Required to leave room for the macro's own routing connections. | Without halo: standard cells crowd the macro edges → router cannot access macro pins → open circuits in the layout (LVS failures). |