Physical Verification

What physical verification proves

PV is a set of checks, each proving a different property. DRC proves the geometry is manufacturable. LVS proves the layout matches the schematic/netlist. Antenna checks prove the layout will survive fabrication. ERC proves the electrical connectivity is sane, and DFM/density checks improve yield. Together they are the contract that lets a foundry commit your GDSII to silicon.

DRC, design rule checking

DRC checks the layout's geometry against the foundry's minimum-feature rules, hundreds to thousands of them at advanced nodes. The core families are simple to picture: spacing (two shapes on a layer must be at least so far apart, or they short), width (a wire cannot be thinner than the minimum, or it fails to print and is EM-weak), and enclosure (a via must be fully surrounded by the metal above and below for a reliable connection). Add minimum-area, density and antenna rules and you have the bulk of a rule deck.

LVS, layout versus schematic

LVS proves the layout is the circuit you meant to build. The tool extracts a netlist directly from the drawn geometry, recognising transistors, resistors and capacitors, and tracing every metal/via connection, then compares that extracted netlist device-by-device and node-by-node against the reference schematic or gate-level netlist. If they match, the layout is electrically the intended circuit. If not, LVS reports exactly where they diverge.

• Short: two nets that should be separate are connected in the layout (the classic, most common LVS error).
• Open: a net that should be one is broken into pieces (often a missing via).
• Missing / extra device: a cell or transistor is absent from, or added to, the layout.
• Property mismatch: a device is there but its size (W/L) or type differs from the schematic.

The antenna effect

During fabrication, metal layers are etched with charged plasma. A long run of metal connected to a transistor gate acts like an antenna, collecting that charge; if enough builds up before the net is tied to a diffusion that could drain it, the charge tunnels through the thin gate oxide and permanently damages the transistor. The risk is captured by the antenna ratio, the collecting metal area divided by the gate-oxide area, which must stay under the foundry limit.

There are two standard fixes. An antenna diode is a small diffusion tied to the net that bleeds the collected charge safely to VSS. A metal jumper reroutes part of the offending net up to a higher layer and back, breaking the long same-layer run into shorter pieces that never accumulate enough charge. Routers insert both automatically during antenna fixing.

ERC and DFM

Two more checks round out signoff. ERC (electrical rule check) catches connectivity mistakes that are legal geometry but bad electrically, floating gates, VDD/VSS shorts, missing well or substrate ties. DFM (design for manufacturability) goes beyond pass/fail rules to improve yield: metal fill to even out density for polishing, and lithography-hotspot and via-doubling checks so marginal patterns print reliably.

The signoff gate

Tape-out is gated on all of these being clean at once: DRC clean, LVS clean, antenna clean, ERC clean, and density satisfied. Only then is the GDSII released to the foundry. In practice PV runs many times through the flow, a quick DRC after routing, full signoff at the end, because the earlier a violation is found, the cheaper it is to fix.