Introduction to Physical Design
Physical Design converts a synthesized gate-level netlist into a manufacturing-ready GDS layout, determining the physical placement, power, clock, and routing o
What Is Physical Design and Why Does It Exist? — After synthesis you have a gate-level netlist - a text file listing cells and connections. But the foundry cannot manufacture a text file. They need a GDS II file - a precise geometric description of every shape of every metal layer at exact X,Y coordinates, measured in nanometers. Physical Design is the entire process of going from that netlist to GDS: figuring out where every cell physically sits on the silicon, how to distribute power to all of them, how to route every wire connecting them, and verifying it all meets manufacturing rules. PD is what transforms your design from "a list of logic" to "a physical chip that can be manufactured."
Physical Design converts a synthesized gate-level netlist into a manufacturing-ready GDS layout, determining the physical placement, power, clock, and routing of all cells.
PD Flow - Click each step to expand details
STEP 1 Floorplanning ▶
Define chip boundary (die area), place macros, I/O pins, and establish power domains. Sets utilization and aspect ratio constraints that guide all subsequent steps.
STEP 2 Power Planning ▶
Create VDD/VSS rings around the core and stripes across the die. Ensure low IR drop and EM-safe current densities throughout the power network.
STEP 3 Placement ▶
Place standard cells within the core area. Global placement minimizes wirelength. Detailed placement legalizes to rows. Timing-driven placement optimizes critical paths.
STEP 4 Clock Tree Synthesis (CTS) ▶
Build a balanced clock distribution network minimizing skew (difference in clock arrival times at flip-flops) and insertion delay. Uses buffers and inverters to drive all clocked elements.
STEP 5 Routing ▶
Connect all cell pins using metal interconnects. Global routing assigns regions. Detail routing assigns actual wires. Must satisfy all DRC rules (spacing, width, via enclosure).
STEP 6 Sign-Off Verification ▶
Run STA with parasitic extraction, DRC (design rule check), LVS (layout vs schematic), and IR drop analysis. All checks must pass before tape-out.