Your First Module

In Verilog, every circuit is wrapped in a module. Think of a module as a box with wires sticking out of it. The wires are called ports. Other circuits connect to your box through those ports.

The smallest useful example

Here is a circuit that takes two inputs and produces their AND. Read it slowly - every word has a job.

// A 2-input AND gate as a module
module and_gate (
  input  wire a,    // an input wire called a
  input  wire b,    // an input wire called b
  output wire y     // an output wire called y
);

  assign y = a & b; // y is always a AND b

endmodule

Reading it piece by piece

• module and_gate ( ... ) - names the box "and_gate" and lists its wires.
• input wire a and input wire b - these are the two wires carrying signals into the box. An AND gate needs two inputs, so we declare both. They behave the same way; b is simply the second input.
• output wire y - y is a wire carrying a signal out of the box.
• assign y = a & b - this is a permanent connection: y is wired to be a AND b, forever and instantly. If a or b changes, y changes too.
• endmodule - closes the box.

Run it without installing anything

You do not need to install tools to start. Open a free simulator in your browser:

1. Go to edaplayground.com and create a free account.
2. Paste your module into the left "design.sv" pane.
3. Pick a simulator (Icarus Verilog is free and fine for learning).
4. You will add a small testbench in a later lesson and press Run to see it work.

If you prefer your own machine, install Icarus Verilog (iverilog) - it is free and open source, and runs on Windows, Linux, and Mac.