Synthesizable RTL and Next Steps
Write code that becomes real hardware - and where to go next
Not every line of Verilog can become a chip. Code that a tool can turn into real gates is called synthesizable. Code that only runs in simulation (like # delays) is not. Knowing the difference is what separates a hobby project from RTL that tapes out.
The synthesizable mindset
| Use freely in RTL | Simulation only - never in RTL |
|---|---|
| assign, always @(*), always @(posedge clk) | #delays (like #5) |
| if/else, case, operators | initial blocks |
| wire, reg, parameters, localparam | $display, $monitor, $finish |
| Flip-flops with clock and reset | Loops that depend on simulation time |
A checklist for clean RTL
- Combinational blocks use always @(*) with blocking = and a default-first assignment.
- Clocked blocks use always @(posedge clk) with non-blocking <=.
- Every flip-flop has a reset to a known value.
- Every case has a default; every combinational output has a default.
- A signal is driven from only one always block.
- Bus widths are explicit and consistent on both sides of an assignment.
Follow this checklist and your code will simulate and synthesize the same way - which is the whole point. Most "it worked in simulation but failed on the board" stories trace back to breaking one of these six rules.
A small project to cement it
Build something end to end on EDA Playground: a 4-bit counter that counts up, holds when a pause input is high, and resets to zero. Write the design, write a testbench that exercises pause and reset, and confirm the waveform matches what you expected. That single exercise uses almost everything in this path.
Where to go next
- Design Verification path - turn your eyeball-the-output testbench into a real, self-checking, randomized verification environment.
- Synthesis path - see how your RTL becomes a gate-level netlist with timing constraints.
- Physical Design path - take a netlist all the way to a manufacturable layout.
Verilog is learned by writing it, not by reading about it. Type the examples yourself, break them on purpose, and watch what the waveform does. The bugs you create and fix here are the fastest teachers you will get.