Module 34 min

DRC - Design Rule Check

DRC verifies that your layout geometry satisfies every manufacturing rule in the foundry's PDK. These rules exist because the lithography and etching processes

DRC verifies that your layout geometry satisfies every manufacturing rule in the foundry's PDK. These rules exist because the lithography and etching processes have physical limits - too-small features simply cannot be manufactured reliably.

Understanding DRC Rule Categories

Rule Category	What It Checks	Why It Exists	Typical Fix
Minimum Width	Wire width ≥ Wmin per metal layer	Too-thin wires break during CMP or have excessive resistance / EM risk	Widen the wire; router usually handles this automatically
Minimum Spacing	Gap between same-layer shapes ≥ Smin	Lithography cannot resolve too-small gaps → shorts between wires	Increase routing track separation; re-route in congested area
Via Enclosure	Metal must extend beyond via edge by min amount on all sides	Overlay (misalignment) in fab could expose via without metal contact	Use larger via enclosure design rule; ensure auto-router uses correct rules
Via Coverage	Minimum number of vias on high-current nets	Single via has limited current capacity; EM requires multiple vias	Replace single-cut vias with via arrays; use via doubling ECO
Notch Rule	Internal notch (concave corner) ≥ Nmin	Narrow notches print incorrectly - corners round off → shape deformation	Fill small notches; ensure polygon merging after fill insertion
Area Rule	Minimum enclosed polygon area	Tiny isolated shapes may not print or etch completely	Remove floating metal shapes; merge small disconnected polygons
Extension Rule	Active/poly must extend beyond diffusion edge	Transistor channel defined by overlap; insufficient extension = no transistor	Standard cell library handles this; flagged in custom analog layout
Density Rules	Min/max metal fill % per window per layer	CMP planarization requires uniform metal density across the wafer	Run fill insertion tool (Calibre Fill); remove excess fill if over-dense
Double-Patterning	Adjacent same-mask shapes must be separable into 2 colors	At <20nm, single lithography cannot print minimum pitch → 2 exposures needed	Assign colors using DP-aware router; fix coloring conflicts
Poly Spacing to Diff	Minimum distance between poly gate and nearby diffusion	Gate coupling to adjacent diffusion can cause leakage or latchup	Handled by standard cell design; appears in custom layout

DRC Violation Examples - Before & After (Annotated)

Click to enlarge

Running DRC with Calibre

SHELL - Calibre DRC Invocation

# Calibre DRC batch run
calibre -drc \
    -hier \                          # hierarchical mode (faster, uses cell caching)
    -turbo 16 \                    # 16 CPU threads parallel
    -64 \                           # 64-bit mode for large designs
    -runset ./drc_runset.svrf \    # DRC rule deck from foundry PDK
    -gds    ./out/chip_final.gds \ # input layout
    -top    chip_top               # top-level cell name

# Key sections in the Calibre runset (.svrf):
DRC RESULTS DATABASE  "drc.results"      ; output DB
DRC SUMMARY REPORT   "drc_summary.rpt"  ; human-readable summary
DRC MAXIMUM RESULTS  1000               ; stop at 1000 per rule (debug mode)
LAYOUT SYSTEM        GDSII

# Check results
grep "RULE" drc_summary.rpt | sort -k3 -rn | head -20
# Shows top 20 rules with most violations  -  fix these first

Pro Tip

Pro DRC Workflow — Don't try to fix DRC violations randomly. Sort by rule then by count - the top 5 rules usually account for 90% of all violations. Fix one rule type at a time using batch ECO scripts. Always re-run DRC after each fix iteration to catch cascading effects (fixing a spacing violation can sometimes introduce a width violation nearby).