DFT and Scan-Aware Synthesis
Building testable logic by stitching flops into scan chains
A chip that cannot be tested cannot be shipped. Design for test (DFT) is woven into synthesis so the manufactured silicon can be checked for defects, and scan insertion is the workhorse of that flow. After fabrication you need to apply a known value to every internal flop and observe what comes out, to catch stuck-at and other manufacturing defects, but normal flops are buried inside the logic and cannot be reached from the pins. Scan solves this by making the flops controllable and observable from a few test pins.
The scan flop and the scan chain
Scan replaces each ordinary flip-flop with a scan flop that has a mux on its D input, selecting between the functional data and a scan-in input under a scan-enable signal. In test mode every scan flop is stitched into a long shift register, the scan chain: data shifts in through scan-in, the chain captures one functional cycle, then the results shift out through scan-out for comparison.
// Behavioral model of the scan flop the tool substitutes in:
// always @(posedge clk)
// q <= scan_enable ? scan_in : data_d; // test vs function
// With scan_enable=1 every flop chains:
// scan_in -> FF -> FF -> FF -> ... -> scan_out
# DFT Compiler: define scan style and test signals, then stitch.
set_scan_configuration -style multiplexed_flip_flop
set_dft_signal -view spec -type ScanEnable -port scan_en -active_state 1
set_dft_signal -view spec -type ScanDataIn -port scan_in
set_dft_signal -view spec -type ScanDataOut -port scan_out
create_test_protocol
dft_drc
insert_dftWhat scan costs you
- Area: the input mux makes a scan flop larger than a plain flop, adding a few percent of cell area across the design.
- Timing: the mux adds delay in front of every flop D pin, and the functional path now passes through it, so setup margin tightens slightly.
- Flow order: synthesize with scan-ready flops and run test DRC before stitching, and run flop-renaming steps like retiming first so the chain is built on stable, final registers.
the interview answer engineers love: scan makes flops controllable and observable by muxing in a shift path, trading a little area and a little setup margin for the ability to test for stuck-at faults. Mentioning that scan insertion must follow retiming, and that DRC must pass before stitching, signals real flow experience.
scan only works if every flop can actually be shifted, so uncontrollable asynchronous resets, gated or internally generated clocks, and combinational feedback can make flops untestable and fail DFT DRC. The fix is to make those resets and clocks controllable from a pin during shift (so DRC passes), and to address the rest at the RTL and clocking level early, because a flop excluded from the chain is a blind spot the tester can never reach.